Tool/software: Linux
We are working with OMAP-L138 processor.
At custom board we use USB2.0 (USB0) interface with external clock from A3 pin (USB_REFCLKIN). During USB initialization I can't wait to get USB0PHYCLKGD bit becomes '1' (CFGCHIP2 register). When this bit is '1', clock must be present, power must be good, and PLL has to be locked. I paste my USB initialization code below. It's based on the code for LCDK board. On custom board USB0 is used as DEVICE, USB1 is not used.
static const short omapl138_usb_pins[] = {
DA850_USB_REFCLKIN,
-1
};
static __init void omapl138_usb_init(void)
{
u32 cfgchip2;
int cnt, ret;
ret = davinci_cfg_reg_list(omapl138_usb_pins);
if (ret)
pr_warn("%s: usb mux setup failed: %d\n", __func__, ret);
cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
/* Setup the Ref. clock frequency for the LCDK at 24 MHz. */
cfgchip2 &= ~CFGCHIP2_REFFREQ;
cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ;
/*
* Select external reference clock for USB 2.0 PHY
* and use it as a clock source for USB 1.1 PHY
* (this is the default setting anyway).
*/
cfgchip2 &= ~CFGCHIP2_USB1PHYCLKMUX;
cfgchip2 &= ~CFGCHIP2_USB2PHYCLKMUX;
/*
* We have to override VBUS/ID signals when MUSB is configured into the
* host-only mode -- ID pin will float if no cable is connected, so the
* controller won't be able to drive VBUS thinking that it's a B-device.
* Otherwise, we want to use the OTG mode and enable VBUS comparators.
*/
cfgchip2 &= ~CFGCHIP2_OTGMODE;
cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN;
cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
cfgchip2 &= ~CFGCHIP2_PHYPWRDN;
cfgchip2 &= ~CFGCHIP2_RESET;
__raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
// while (!(__raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)) & CFGCHIP2_PHYCLKGD));
cnt = 10;
while (cnt) {
cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
if (cfgchip2 & CFGCHIP2_PHYCLKGD)
break;
msleep(50);
cnt--;
}
if (cnt == 0) {
pr_err("%s: usb clock or power is not good (0x%08X)!\n", __func__, cfgchip2);
return;
}
/*
* TPS2065 switch @ 5V supplies 1 A (sustains 1.5 A),
* with the power on to power good time of 3 ms.
*/
ret = da8xx_register_usb20(1000, 3);
if (ret)
pr_warn("%s: USB 2.0 registration failed: %d\n", __func__, ret);
// if (HAS_OHCI)
// da8xx_board_usb_init(da850_lcdk_usb11_pins,
// &omapl138_lcdk_usb11_pdata);
return;
}
At custom board we have following USB connections:
Signal Name Connect To
USB0_DM USB0 PHY data minus (USB connector)
USB0_DP USB0 PHY data plus (USB connector)
USB0_VDDA33 +3.3 V
USB0_ID No connection
USB0_VBUS VBUS (USB connector)
USB0_DRVVBUS No connection
USB_REFCLKIN 24 MHz oscillator
USB0_VDDA18 +1.8 V
USB0_VDDA12 0.22 uF to GND
USB_CVDD +1.3 V
USB1_DM No connection
USB1_DP No connection
USB1_VDDA33 No connection
USB1_VDDA18 No connection
Why we can't get CFGCHIP2_PHYCLKGD (Bit 17) to be '1'? What is wrong?
