TMS320C6722B: What Maximum Clock Frequency can we generate in GPIO pins?

Hello Yordan,

Thanks for your reply.
As par the table, If OSCIN is 25Mhz then the SYSCLK maximum Output frequency is
1. SYSCLK1: 300Mhz
2. SYSCLK2: 150Mhz
3. SYSCLK3: 75Mhz
4. AUXCLK: 25Mhz. All these correct?

GPIO- Couple of MHz, So What is the maximum frequency?

Regards,
Naveen

Hi Yordan,

Thanks for the information.

I need to provide clock to FPGA, So What is the Frequency i can generate from ACLKX0  pin no.142? 

Regards,

Naveen K

Hi,

Thanks for the information.

I need to provide clock to FPGA, So What is the Frequency range i can generate from ACLKX0  pin no.142? 

Kindly advice.

Regards,

Naveen K

Dear Yordan,

Thank you very much for your response.

I have read all datasheet, I understand something but i had some confusions and doubts. That's why am getting confirmation with you.

In datasheet its mentioned the pins is for Multi-channel Audio Serial Port or we can use as GPIO pins.

But am using this pins for providing the clock for FPGA internal operation. So bit doubts.

As par the datasheet i can provide maximum 25Mhz from AUX pins.

My straight question is, 1. Can i provide 25Mhz continuously from AUX pin(ACLKX0) to FPGA for its internal PLL operations and even if not for data transmission  ?

2. Including above case, Can i also use same clock source i.e from the same pin (ACLKX0) for all data transmission from the GPIO pins(AXRO) or simply call serial data pins.

 

Kindly Provide your advice for both 2 questions individually.

 

Regards,

Naveen

Hello Yordan,

Thank you very much for your support.

1. Could you advice, Is there any other clock source for providing continuous clock to the FPGA? & Could you suggest How i can interface DSP and FPGA for data transmission and receiving.What maximum speed i can achieve.

2. For ACLKX0, we can generate Clock internally and provide to the external device. As par the datasheet,
we can also use external device clock for ACLKXO right? So ACLKXO pin is for both Transmiting or receiving CLOCK right?

3. If i want to receive data, i need to use ACLKR0 or i can also use ACLKX0 for receiving data? I studied datasheet but confusing because different clk for RX or TX.

Kindly Advice for these.

Regards,
Naveen K

Dear Yordan,

Thanks for the information. It's very helpfull.

1. As par the datasheet, EMIF is only for Memory interface right? Even we can't configure as GPIO pins right?

2. As par the datasheet diagram (page 47), i have connected FLASH and SDRAM to DSP. Now i have to interface FPGA and DSP.
How to Interface DSP EMIF and FPGA ? Kindly advice.

May be i can use 16bit parallel interface right? If yes, then address pins?

3. Kindly provide any schematics and application note related to my application( DSP-FPGA-FLASH-SDRAM).

4. Regarding to MCASP, i studied both datasheets, As par datasheet, We can use either internal(DSP) clock or external device clock source and same clock is used for either receiving or Transmitting or both.

Appreciate your support.

Regards,
Naveen K