66AK2L06: JESD Interface Rate - Difference

Mehmet

Expert 1255 points

Part Number: 66AK2L06
Other Parts Discussed in Thread: ADC14X250, , RFSDK

Hi,

We try to sample analog signal.

We used RFSDK 2.03. And we succeed to run playback demo properly.

Then, we select 1x1-1xLTE80DEMO2-HC-JESD121121x DFE configuration.

But we we could not sample analog signal.

My question is : RFSDK2 DEMO2 Status-Control Page JESD Interface Rate is 245.76 Msps.

But our custom design board can produce 240Mhz clock

So ADC14X250 CLKIN signal 240Mhz clock.

Does this difference (240mhz vs 245.76mhz) cause that we cannot sample analog signal ?

over 5 years ago

0 Radio-Joe over 5 years ago

TI__Mastermind 37500 points

The clock rate has to be the proper sample rate for the signal processing to show a proper signal.
There should be a clock that develops the JESD Serdes rate, and another clock for the ADC sample rate,
these need to be locked together. Please rework your clock, or substitute an external clock locked to your reference.

Also there is the DFE GEL file, to check if the JESD status is correct, this indicates that the ADC data is being received.
If there is a JESD error, the data will be zeroed based on the JESD logic.
Regards,
Joe Quintal

0 Mehmet over 5 years ago in reply to Radio-Joe

Expert 1255 points

Hi Joe,

We solved clock differences problem. But we cannot sample analog signal again..

As you said, we tried DFE GEL file.

Results :

script ---> JESD_CHECK_ALL
C66xx_1: GEL Output: ==============
C66xx_1: GEL Output: JESD_Check_All
C66xx_1: GEL Output: ==============
C66xx_1: GEL Output: JESDTX Lane 0 enabled, assigned to TX Link 0
C66xx_1: GEL Output: JESDTX Lane 1 enabled, assigned to TX Link 0
C66xx_1: GEL Output: JESDRX Lane 0 enabled, assigned to RX Link 0
C66xx_1: GEL Output: ERROR: JESDTX Link 0 SYSREF error
C66xx_1: GEL Output: ERROR: JESDTX Lane 0 sync_state = 0 (SYNC) - waiting for sync request, transmitting commas
C66xx_1: GEL Output: ERROR: JESDTX Lane 0 sync_state = 0 (SYNC) - waiting for sync request, transmitting commas
C66xx_1: GEL Output: WARNING: JESDRX Lane 0 FIFO empty flag asserted.
C66xx_1: GEL Output: ERROR: JESDRX Lane 0 FIFO read error asserted.
C66xx_1: GEL Output: ERROR: JESDRX Link 0 SYSREF error
C66xx_1: GEL Output: ERROR: JESDRX Lane 0 cs_state = 0 (INIT) - waiting for commas, assert sync request
C66xx_1: GEL Output: ERROR: JESDRX Lane 0 fs_state = 0 (INIT) - sync request asserted or still receiving commas
C66xx_1: GEL Output: INFO: JESDRX Link 0 has a skew of 0 between the earliest and latest lanes.





script --->  Check_JESD_Status 
C66xx_1: GEL Output: JESDTX status 
C66xx_1: GEL Output: JESDTX FIFO error lane 0 = 0x00000000 
C66xx_1: GEL Output: JESDTX FIFO error lane 1 = 0x00000000 
C66xx_1: GEL Output: JESDTX FIFO error lane 2 = 0x00000000 
C66xx_1: GEL Output: JESDTX FIFO error lane 3 = 0x00000000 
C66xx_1: GEL Output: ERROR: JESDTX Link 0 SYSREF error
C66xx_1: GEL Output: ERROR: JESDTX Link 1 SYSREF error
C66xx_1: GEL Output: JESDTX First Sync Request (should be 1) = 0x00000011 
C66xx_1: GEL Output: JESDTX Sync State = 0x00000000 
C66xx_1: GEL Output: JESDRX status 
C66xx_1: GEL Output: JESDRX FIFO error lane 0 = 0x00000300 
C66xx_1: GEL Output: JESDRX FIFO error lane 1 = 0x00000000 
C66xx_1: GEL Output: JESDRX FIFO error lane 2 = 0x00000000 
C66xx_1: GEL Output: JESDRX FIFO error lane 3 = 0x00000000 
C66xx_1: GEL Output: ERROR: JESDRX Link 0 SYSREF error
C66xx_1: GEL Output: ERROR: JESDRX Link 1 SYSREF error
C66xx_1: GEL Output: JESDRX CS STATUS = 0x00000000 
C66xx_1: GEL Output: JESDRX FS STATUS = 0x00000000 
C66xx_1: GEL Output: JESDRX lane 0, status = 0x00000000 
C66xx_1: GEL Output: JESDRX lane 1, status = 0x00000000 
C66xx_1: GEL Output: JESDRX lane 2, status = 0x00000000 
C66xx_1: GEL Output: JESDRX lane 3, status = 0x00000000 
C66xx_1: GEL Output: INFO: JESDRX Link 0 has a skew of 0 between the earliest and latest lanes.
C66xx_1: GEL Output: INFO: JESDRX Link 1 has a skew of 0 between the earliest and latest lanes.

We apply 120khz LVDS clock to LAMARR_PROCESSOR_0 AF30-AE30 pins ( like 66AK2L06 Evaluation Module )

We configure ADC14X250 register address 0x12 with value 0x81

and We apply ADC14X250 device clock 245 MHZ

we dont apply SYSREF to the ADC14X250 .

What could be the problem?

Thanks

0 Radio-Joe over 5 years ago in reply to Mehmet

TI__Mastermind 37500 points

Hello,
The ADC clock must be 245.76Mhz.

In the JESD troubleshooting when you have a Rx FIFO status other than 0, the initial JESD setup has failed, you must restart the whole process.

So following the Getting Started and User Guide, you have configured the external ADC14x250, then started the RFSDK.

The SYSREF signal also shows an error, this can help to cause problems. If you are not using SYSREF at the ADC14x250, go back to the internally generated SYSREF from the 66aK2L06 EVM. On the EVM you have a clock generator that generates the 122.88MHz on the board going to 66aK2L06, you can change the FMC connector clock to 245.76Mhz, but changing the clock divider value.

You then need to connect or reroute the differential 245.76 Mhz clock to the ADC.

All of the clocks need to be locked together. The serdes high rates, need to be well matched.

The DFE GEL file, any time there is JESD Rx FIFO error other than 0, you must restart.

Work on removing the SYSREF error, this will cause problems for DFE as well.
Work on removing the DFE-JESD Rx FIFO error, the current software does not recover from this and needs restart of RFSDK.

Regards,
Joe Quintal

0 Radio-Joe over 5 years ago in reply to Radio-Joe

TI__Mastermind 37500 points

Hello,

I received a note you have rejected the answer. I don't know what additional steps you have done, the clocks are not adjustable,

the serdes rate on the 66Ak2L06 is developed from a 122.88Mhz clock. You can look on the High Speed Products - Data converter forum, but I think

the ADC14x250 requires a clock that hs the ADC sample rate. The 66aK2L06 serides rate, sample rate, JESD mode, must match between the ADC and the DFE-in 66aK2L06.

Regards,

Joe Quintal

0 Mehmet over 5 years ago in reply to Radio-Joe

Expert 1255 points

Hi Joe,

We ensure the ADC clock 245.76Mhz.

And then we checked other clocks. We did not find the problem.

Then i rejected your answer.

But we noticed something may be important.

EVMK2L Evaluation Module SOC (TCI6630K2L) device speed range --> 1.2GHZ

Our custom design board SOC (66AK2L06) device speed range --> 1GHZ

We ported EVMK2L Evaluation Modules BMC source code to our custom design board,
And also we copied LMK and ADC settings. We did not change any settings.

Could device speed ranges differences be the problem ?

Thanks for your help and patience Joe

0 Radio-Joe over 5 years ago in reply to Mehmet

TI__Mastermind 37500 points

Hello,
The device speed range Main PLL, and ARM PLL should be set for the device you need. This is part of Uboot.

Related to RFSDK, as long as the 122.88Mhz for the 66ak2l06, 122.88Mhz for the Serdes clock, 245.76Mhz are harmonically locked
the clock should be OK.

Sysref, needs to come from the divided 122.88Mhz clock, it is typically a power of 2 multiple of F, to achieve JESD lock you need to send this
signal to both the ADC and to the 66aK2L06 SYSREF. There is a special FAE alert for 66aK2L06 SYSREF, it is attached.

You need to initially program the ADC. As you begin to bringup RFSDK, eventually the DFE configuration tries to bring up JESD Tx and JESD Rx.
In your special configuration, JESD Tx should be ignored. JESD Rx, the SYSREF should align the start of Frame counting, and you should see the JESD SYNCOUT be '0' from 66aK2L06 to the ADC14x250. Once the ADC data is received on JESD lane 0, the Sync pattern received causes the JESD SYNCOUT on the 66aK2L06 to be a '1', then the ILA sequence starts. So after this point in tracing the RF On state, check the GEL file for the JESD status, for Rx noSYSREF errors, and JESD Rx FIFO status needs to be 0. Only then will Rx data received be based to the DFE Rx for signal processing.

If you can't get JESD Rx FIFO0 to be 0, make sure the ADC port is wired to the proper JESD Serdes. This can be changed but needs a different DFE configuration, and a different RFSDK radio select, and use case. Look at the User Guide, and Getting Started Guide.

On your board, you can try this with the JESD loopback configuration first, this will tell you if the digital portion without the ADC is working.

Regards,
Joe QUintal

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66AK2L06: JESD Interface Rate - Difference