TMS320C6655: instability due to DDR configuration

Joakim Jarfjord

Part Number: TMS320C6655

Hi,

My customer is struggling with difficulties to get stable performance on their design, which seems to be related to the DDR configuration. Can someone please help us to verify the configuration below:

Settings of DDR3 SDRAM CK=666.67MHz; tCK=1/CK=1.500ns; tRCD=tRP=CL=13.75ns; Speed -125 (1.25ns or 800MHz)

DDR memory is: TN-47-02 DDR2 from Micron (www.micron.com/.../tn4702.pdf)

OLD SETTINGS: Two Versions in step (iv).

(i) CL=floor(13.75n/(1/666.67M))=9=0x9

(ii) CWL=7 (0x7) since 1.875ns>^tCK>1.500ns

(iii) AL arbitrarily set via step (iv) and not equal to 0, CL-1 or CL-2.

(iv) DDR_PHY_CTRL_1[4:0]=[10=0x0A|14=0x0E] with 0x0A older and 0x0E being newer settings thus RL=CL+AL=[10+1=11=0xC|14+1=15=0xF]

Latest NEW SETTINGS

(i) CL=ceiling(13.75n/(1/666.67M))=10=0xA

(ii) CWL=7 (0x7) since 1.875ns>^tCK>1.500ns

(iii) Selected AL=CL-2=10-2=8=0x8 to meet DDR_PHY_CTRL_1[4:0] value constraint.

(iv) DDR_PHY_CTRL_1[4:0]=17=0x11 (Register value required is 18-1=17=0x11).This meets CL+1=10+1=11<=Register Value<=CL+7=10+7=17

We would like you to review the latest settings in (2) and also possibly comment on the settings in older versions in (1). We are experiencing AC power drops from large fixed FFT size computation from captured samples with instability of >=0.3/0.5dB, over multiple sample intervals in time (few hours to a couple of days), and moving from older settings to new settings we have improved the instability – but still needs further improvement. What is the implication of improper setting of CL and specifically AL (Posted CAS Additive Latency) with respect to data gap (excerpt from pp15-16 TN4702.pdf from Micron Tech. Inc.), and its impact on data read out from DDR3.

Best regards,

Joakim

over 6 years ago

0 Tom Johnson 16214 over 6 years ago

TI__Mastermind 46460 points

Joakim,

There is a REG_CALC spreadsheet tool available to perform those calculations. It is associated with the Applications Note SPRABL2 at .

DDR commissioning on C6655 is a multi-step process where all steps must be completed in order. This is summarized in the following wiki page:

Please post the length matching report and your completed PHY_CALC and REG_CALC spreadsheets for review.

Tom

0 Joakim Jarfjord over 6 years ago in reply to Tom Johnson 16214

TI__Expert 4710 points

Hi Tom,

Attaching an excel sheet with all the requested information merged together.

This is for the current settings:

Settings of DDR3 SDRAM CK=666.67MHz; ^tCK=1/CK=1.500ns; ^tRCD=^tRP=CL=13.75ns; Speed -125 (1.25ns or 800MHz).

In essence, the customer just needs to know how best to calculate CL/CWL/AL/RL/WL latency, as this seems to us to be independent selection, only based on DDR3 CK, ^tRCD=^tRP=CL and speed grade.

Thanks,

Joakim

DDR3 PHY Calc and DDR3 Register Calcv10172018.xlsx

Settings of DDR3 SDRAM CK=666.67MHz; ^tCK=1/CK=1.500ns; ^tRCD=^tRP=CL=13.75ns; Speed -125 (1.25ns or 800MHz).

0 Tom Johnson 16214 over 6 years ago in reply to Joakim Jarfjord

TI__Mastermind 46460 points

Joakim,

I am not able to validate the equations in the extra tabs added to the PHY_CALC worksheet. The REG_CALC worksheet contains the equations that have been carefully validated. I will insert the information that you are asking in the REG_CALC worksheet so that you can see the expected result.

Since you did not provide an exact datasheet part number, I have pulled down the MT41K1G8SN-125 IT datasheet from the Micron website as an example. It is an x8 device in speed grade -125. You will need to refer to the DDR3L-1600 speed bins table on page 70 for this device. Since you are operating it at 1333MT/s with a clock of 666MHz that has a period of 1.5ns, you would use CL=9 and CWL=7. (You could also use CL=10 and CWL=7.) Also from this table you get the values for:

T_RCD = 13.75
T_RP = 13.75
T_RC = 48.75
T_RAS = 35

The remainder of the values come from Table 54 starting on page 73 from the DDR-1600 column.

T_WR = 15
T_FAW = 40
T_WTR = max(4*CK,7.5) = 7.5
T_XP = max(3*CK,6) = 6
T_XS = t_RFC + 10 = 360
T_XSDLL = 512
T_RTP = max(4*CK,7.5) = 7.5
T_CKE = max(3*CK,5) = 5
T_CKESR = T_CKE + CK = 6.5
T_ZQCS = 64
T_RFC = 350

Since I chose an 8Gb x8 part, the ROWSIZE is 16 bits and the PAGESIZE is 2048 words. Also, I selected the 32-bit bus width since this is C6655. The attached spreadsheet has these values entered. You can see the equations used to calculate the register values. Please let me know if you have any questions.

Tom

DDR3 Register Calc v4 E2E.xlsx

0 Tom Johnson 16214 over 6 years ago in reply to Tom Johnson 16214

TI__Mastermind 46460 points

Joakim,

Also note that I cannot validate the contents in the PHY_CALC worksheet without the length matching report described in the wiki.

Tom

0 Joakim Jarfjord over 6 years ago in reply to Tom Johnson 16214

TI__Expert 4710 points

Hi Tom,

Thanks for helping out here. Please see below follow up questions/comments from the customer.

Best regards, Joakim

------------------

Please find attached Micron Technology Inc data sheet “4Gb_DDR3L.pdf” with applicable part MT41K256M16HA-125-E. We need clarification on the following. We are operating at CK=666.67MHz (tCK=1.5ns) at Data Rate 1333 MT/s (666.67x2MHz) with DDR3 SDRAM ^tRCD=^tRP=CL=13.75ns, Speed Grade -125 (1.25ns or 800MHz) NOT Speed Grade -15E with Data Rate 1333 MT/s, ^tRCD=^tRP=CL=13.5ns. Or is that since we are operating at CK=666.67MHz (tCK=1.5ns) at Data Rate 1333 MT/s, this translates to Data Rate 1333 MT/s, ^tRCD=^tRP=CL=13.5ns?

After we have defined CL=9 or 10/CWL=7, how do we select AL (Posted CAS Additive Latency) to then set RL=CL+AL and WL=CWL+AL?

We will look at “DDR3 Register Calc v4 E2E.xlsx” with the settings (same as used in MT41K256M16HA-125-E):

T_RCD = 13.75

T_RP = 13.75

T_RC = 48.75

T_RAS = 35

To enable validation of contents in the PHY_CALC worksheet, please find attached the length matching report in “8DG62442_Length_Summary.txt”. We look forward to your response and Tom’s.

8DG62442_Length_Summary.txt

=======================================================================
Xpedition xPCB Layout Review Hazards Report
=======================================================================
Length_Summary Hazard Report:
File : C:\Projects\8DG62443AANG01_G01_VX_VIPPO_180327\PCB\LogFiles\Length_Summary.txt
Wed Oct 17 13:56:04 2018


% Meander  : 0.00

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_CLK_N  1.91655     0           0.00      DDR_Diff  DDR              


% Meander  : 0.00

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_CLK_P  1.92151     0           0.00      DDR_Diff  DDR              


% Meander  : 41.03

Net Name    Length (in) Meander (in) % Meander Net Class Constraint Class 
=========== =========== ============ ========= ========= ================ 
DDR_DQS_0_N  0.88836     0.25844     41.03     DDR_Diff  DDR/DDR_DQ0      


% Meander  : 40.14

Net Name    Length (in) Meander (in) % Meander Net Class Constraint Class 
=========== =========== ============ ========= ========= ================ 
DDR_DQS_0_P  0.88278     0.25286     40.14     DDR_Diff  DDR/DDR_DQ0      


% Meander  : 131.21

Net Name    Length (in) Meander (in) % Meander Net Class Constraint Class 
=========== =========== ============ ========= ========= ================ 
DDR_DQS_1_N  0.87388     0.49593     131.21    DDR_Diff  DDR/DDR_DQ1      


% Meander  : 99.66

Net Name    Length (in) Meander (in) % Meander Net Class Constraint Class 
=========== =========== ============ ========= ========= ================ 
DDR_DQS_1_P  0.8804      0.43945     99.66     DDR_Diff  DDR/DDR_DQ1      


% Meander  : 57.76

Net Name    Length (in) Meander (in) % Meander Net Class Constraint Class 
=========== =========== ============ ========= ========= ================ 
DDR_DQS_2_N  0.99996     0.36611     57.76     DDR_Diff  DDR/DDR_DQ2      


% Meander  : 57.25

Net Name    Length (in) Meander (in) % Meander Net Class Constraint Class 
=========== =========== ============ ========= ========= ================ 
DDR_DQS_2_P  0.99675     0.36289     57.25     DDR_Diff  DDR/DDR_DQ2      


% Meander  : 75.04

Net Name    Length (in) Meander (in) % Meander Net Class Constraint Class 
=========== =========== ============ ========= ========= ================ 
DDR_DQS_3_N  0.99927     0.4284      75.04     DDR_Diff  DDR/DDR_DQ3      


% Meander  : 73.96

Net Name    Length (in) Meander (in) % Meander Net Class Constraint Class 
=========== =========== ============ ========= ========= ================ 
DDR_DQS_3_P  0.9931      0.42223     73.96     DDR_Diff  DDR/DDR_DQ3      


% Meander  : 86.94

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQM_0  0.8832      0.41075     86.94     DDR_DQ    DDR/DDR_DQ0      


% Meander  : 21.39

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQM_1  0.87938     0.15497     21.39     DDR_DQ    DDR/DDR_DQ1      


% Meander  : 0.42

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQM_2  0.88955     0.00372     0.42      DDR_DQ    DDR/DDR_DQ2      


% Meander  : 66.82

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQM_3  1.00488     0.40252     66.82     DDR_DQ    DDR/DDR_DQ3      


% Meander  : 64.68

Net Name Length (in) Meander (in) % Meander Net Class Constraint Class 
======== =========== ============ ========= ========= ================ 
DDR_DQ_0  0.88177     0.34634     64.68     DDR_DQ    DDR/DDR_DQ0      


% Meander  : 76.19

Net Name Length (in) Meander (in) % Meander Net Class Constraint Class 
======== =========== ============ ========= ========= ================ 
DDR_DQ_1  0.88789     0.38396     76.19     DDR_DQ    DDR/DDR_DQ0      


% Meander  : 22.38

Net Name Length (in) Meander (in) % Meander Net Class Constraint Class 
======== =========== ============ ========= ========= ================ 
DDR_DQ_2  0.88653     0.16212     22.38     DDR_DQ    DDR/DDR_DQ0      


% Meander  : 88.70

Net Name Length (in) Meander (in) % Meander Net Class Constraint Class 
======== =========== ============ ========= ========= ================ 
DDR_DQ_3  0.8915      0.41906     88.70     DDR_DQ    DDR/DDR_DQ0      


% Meander  : 13.89

Net Name Length (in) Meander (in) % Meander Net Class Constraint Class 
======== =========== ============ ========= ========= ================ 
DDR_DQ_4  0.89676     0.10936     13.89     DDR_DQ    DDR/DDR_DQ0      


% Meander  : 35.37

Net Name Length (in) Meander (in) % Meander Net Class Constraint Class 
======== =========== ============ ========= ========= ================ 
DDR_DQ_5  0.89534     0.23392     35.37     DDR_DQ    DDR/DDR_DQ0      


% Meander  : 47.37

Net Name Length (in) Meander (in) % Meander Net Class Constraint Class 
======== =========== ============ ========= ========= ================ 
DDR_DQ_6  0.8819      0.28347     47.37     DDR_DQ    DDR/DDR_DQ0      


% Meander  : 52.51

Net Name Length (in) Meander (in) % Meander Net Class Constraint Class 
======== =========== ============ ========= ========= ================ 
DDR_DQ_7  0.91266     0.31423     52.51     DDR_DQ    DDR/DDR_DQ0      


% Meander  : 47.45

Net Name Length (in) Meander (in) % Meander Net Class Constraint Class 
======== =========== ============ ========= ========= ================ 
DDR_DQ_8  0.88235     0.28392     47.45     DDR_DQ    DDR/DDR_DQ1      


% Meander  : 33.00

Net Name Length (in) Meander (in) % Meander Net Class Constraint Class 
======== =========== ============ ========= ========= ================ 
DDR_DQ_9  0.8797      0.21828     33.00     DDR_DQ    DDR/DDR_DQ1      


% Meander  : 114.66

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_10  0.8789      0.46945     114.66    DDR_DQ    DDR/DDR_DQ1      


% Meander  : 39.48

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_11  0.92256     0.26115     39.48     DDR_DQ    DDR/DDR_DQ1      


% Meander  : 78.34

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_12  0.89873     0.39479     78.34     DDR_DQ    DDR/DDR_DQ1      


% Meander  : 47.11

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_13  0.88034     0.28191     47.11     DDR_DQ    DDR/DDR_DQ1      


% Meander  : 99.07

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_14  0.87779     0.43685     99.07     DDR_DQ    DDR/DDR_DQ1      


% Meander  : 86.29

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_15  0.88011     0.40767     86.29     DDR_DQ    DDR/DDR_DQ1      


% Meander  : 36.11

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_16  0.99136     0.26302     36.11     DDR_DQ    DDR/DDR_DQ2      


% Meander  : 31.21

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_17  0.99703     0.23718     31.21     DDR_DQ    DDR/DDR_DQ2      


% Meander  : 36.25

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_18  0.99236     0.26401     36.25     DDR_DQ    DDR/DDR_DQ2      


% Meander  : 14.98

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_19  1.01853     0.1327      14.98     DDR_DQ    DDR/DDR_DQ2      


% Meander  : 49.72

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_20  0.99614     0.33079     49.72     DDR_DQ    DDR/DDR_DQ2      


% Meander  : 8.83

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_21  0.99835     0.08103     8.83      DDR_DQ    DDR/DDR_DQ2      


% Meander  : 43.10

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_22  0.99718     0.30033     43.10     DDR_DQ    DDR/DDR_DQ2      


% Meander  : 5.72

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_23  1.00306     0.05424     5.72      DDR_DQ    DDR/DDR_DQ2      


% Meander  : 31.02

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_24  0.99557     0.23572     31.02     DDR_DQ    DDR/DDR_DQ3      


% Meander  : 69.16

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_25  1.01893     0.41657     69.16     DDR_DQ    DDR/DDR_DQ3      


% Meander  : 65.78

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_26  0.99862     0.39626     65.78     DDR_DQ    DDR/DDR_DQ3      


% Meander  : 126.74

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_27  1.00871     0.56382     126.74    DDR_DQ    DDR/DDR_DQ3      


% Meander  : 28.97

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_28  0.73626     0.1654      28.97     DDR_DQ    DDR/DDR_DQ3      


% Meander  : 110.89

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_29  1.00463     0.52825     110.89    DDR_DQ    DDR/DDR_DQ3      


% Meander  : 45.70

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_30  0.96943     0.30407     45.70     DDR_DQ    DDR/DDR_DQ3      


% Meander  : 76.45

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_DQ_31  1.00729     0.43642     76.45     DDR_DQ    DDR/DDR_DQ3      


% Meander  : 0.00

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_ADDR0  2.28845     0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_ADDR1  2.14367     0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_ADDR2  2.16718     0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_ADDR3  2.32976     0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_ADDR4  2.11938     0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_ADDR5  2.34017     0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_ADDR6  2.10624     0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_ADDR7  2.28989     0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_ADDR8  2.08535     0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_ADDR9  2.13256     0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name   Length (in) Meander (in) % Meander Net Class Constraint Class 
========== =========== ============ ========= ========= ================ 
DDR_ADDR10  2.23255     0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name   Length (in) Meander (in) % Meander Net Class Constraint Class 
========== =========== ============ ========= ========= ================ 
DDR_ADDR11  2.07057     0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name   Length (in) Meander (in) % Meander Net Class Constraint Class 
========== =========== ============ ========= ========= ================ 
DDR_ADDR12  2.15067     0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name   Length (in) Meander (in) % Meander Net Class Constraint Class 
========== =========== ============ ========= ========= ================ 
DDR_ADDR13  2.0903      0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name   Length (in) Meander (in) % Meander Net Class Constraint Class 
========== =========== ============ ========= ========= ================ 
DDR_ADDR14  2.16725     0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name   Length (in) Meander (in) % Meander Net Class Constraint Class 
========== =========== ============ ========= ========= ================ 
DDR_ADDR15  2.1886      0           0.00      DDR_QALL  DDR/DDR_CMD      


% Meander  : 0.00

Net Name   Length (in) Meander (in) % Meander Net Class Constraint Class 
========== =========== ============ ========= ========= ================ 
DDR_BANK_0  2.31947     0           0.00      DDR_QALL  DDR/DDR_BANK0_2  


% Meander  : 0.00

Net Name   Length (in) Meander (in) % Meander Net Class Constraint Class 
========== =========== ============ ========= ========= ================ 
DDR_BANK_1  2.07581     0           0.00      DDR_QALL  DDR/DDR_BANK0_2  


% Meander  : 0.00

Net Name   Length (in) Meander (in) % Meander Net Class Constraint Class 
========== =========== ============ ========= ========= ================ 
DDR_BANK_2  2.29277     0           0.00      DDR_QALL  DDR/DDR_BANK0_2  


% Meander  : 0.00

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_CAS_N  2.30418     0           0.00      DDR_QALL  DDR/DDR_CNTL     


% Meander  : 0.00

Net Name Length (in) Meander (in) % Meander Net Class Constraint Class 
======== =========== ============ ========= ========= ================ 
DDR_CK_E  2.15129     0           0.00      DDR_QALL  DDR/DDR_CNTL     


% Meander  : 0.00

Net Name Length (in) Meander (in) % Meander Net Class Constraint Class 
======== =========== ============ ========= ========= ================ 
DDR_CS_N  2.3403      0           0.00      DDR_QALL  DDR/DDR_CNTL     


% Meander  : 0.00

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_ODT_0  2.33638     0           0.00      DDR_QALL  DDR/DDR_CNTL     


% Meander  : 0.00

Net Name  Length (in) Meander (in) % Meander Net Class Constraint Class 
========= =========== ============ ========= ========= ================ 
DDR_RAS_N  2.28631     0           0.00      DDR_QALL  DDR/DDR_CNTL     


% Meander  : 9.14

Net Name    Length (in) Meander (in) % Meander Net Class Constraint Class 
=========== =========== ============ ========= ========= ================ 
DDR_RESET_N  1.5194      0.12728     9.14      DDR_QALL  Power            


% Meander  : 0.00

Net Name Length (in) Meander (in) % Meander Net Class Constraint Class 
======== =========== ============ ========= ========= ================ 
DDR_WE_N  2.26523     0           0.00      DDR_QALL  DDR/DDR_CNTL

0 Tom Johnson 16214 over 6 years ago in reply to Joakim Jarfjord

TI__Mastermind 46460 points

Joakim,

Why are you asking about the value calculated for Additive Latency? None of the PHY or Controller registers request this number for customer input. As you can see in the REG_CALC spreadsheet, this is not requested.

If you refer to the Keystone Architecture DDR3 Memory Controller User's Guide (SPRUGV8E) on page 33, it discusses how the Extended Mode Register 1 value is composed by the SDRAM initialization logic. The Additive Latency bitfield [4:3] is set to [00].

Tom

0 Tom Johnson 16214 over 6 years ago in reply to Tom Johnson 16214

TI__Mastermind 46460 points

Joakim,

Regarding the length report provided - this file does not contain the required information. Please refer to the examples provided in the wiki. A report is needed that shows that the routing rules are met. The level of detail shown in the sample reports is mandatory.

Tom

0 Joakim Jarfjord over 6 years ago in reply to Tom Johnson 16214

TI__Expert 4710 points

Hi Tom,

Update from the customer:

------------

We will provide completed KeyStone_DDR3_Length_Rules_Template.zip: “KeyStone DDR3 Length Rules Template v1p0.xlsx” to provide complete required information for Tom.

We are now clear on the usage of “DDR3 PHY Calc v11.xlsx” and “DDR3 Register Calc v4.xlsx” and just have to align on “KeyStone DDR3 Length Rules Template v1p0.xlsx”, thank you.

In C6655 Keystone Architecture DDR3 Memory Controller: User’s Guide: sprugv8e.pdf (November 2010-Revised 2015) page 80, there is a define requirement of READ_LATENCY=RL=CL+AL with CL+1<=RL<=CL+7 (register value 1 less desired value). The JESD79-3C (as contained in Micron data sheet “4Gb_DDR3L.pdf”, sent separately previously) Mode Registers [0:3] requirements at Mode Register 1, requires defining AL as either (binary) (1) A[4:3]=00 = 0=(AL disabled) (2) A[4:3]=01 =CL-1 or (3) A[4:3]=10 =CL-2 (4) A[4:3]=11 =Reserved. The setting of RL replaces the default value of 0x0 in AL is our thinking. If you could comment on our assessment here, as we think AL may not be always 0x0, depending on the setting of RL which has as an implied assign to AL.

--------------

Thanks,

Joakim

0 Tom Johnson 16214 over 6 years ago in reply to Joakim Jarfjord

TI__Mastermind 46460 points

Joakim,

I originally thought the question was about the Additive Latency bits that are programmed into the DDR3 SDRAM Extended Mode Register 1. We have established that for C665x devices, the DDR Controller programs these bits to [00] during initialization and that these bits are not customer programmable. This is documented in Table 2-14 of the Keystone Architecture DDR3 Memory Controller User's Guide (SPRUGV8E) on page 33.

I now understand that you are asking about the READ_LATENCY bit field in the DDR PHY Control 1 Register (DDR_PHY_CTRL_1) which is discussed in Section 4.23 of the same document on page 80. It has the following description:

This field defines the read latency from DDR SDRAM in terms of DDR3 clock cycles. The value depends on the CAS latency used. The user can choose any value between max and min values given below. The programmed value should always be programmed as the chosen value minus one.

- Maximum value possible = CAS latency + 7
- Minimum value possible = CAS Latency + 1

I do not see where you got the equation shown above in your post. I have checked every version of SPRUGV8 back to its original release and they all say the same thing.

This bit field is part of the DDR PHY Control 1 Register. This is because it is a term related to PHY leveling. This READ_LATENCY field is a write to read turn-around delay that is the sum of the CAS Write Latency plus the longest round-trip leveling delay. Therefore, it is dependent on the board design. Please refer to the DDR_PHYCTRL discussion at the bottom of page 10 of the KeyStone I DDR3 Initialization Application Report (SPRABL2E).

DDR_PHYCTRL, also known as DDR_PHY_CTRL_1 or DDR_PHYC, programs termination modes for the output buffers and the read latency in the lower five bits. The values supported in the upper bits are given and cannot be changed on customer designs. The read latency is somewhat based on board layout. A conservative value for it is CL+3 because the controller can operate with up to four clocks of round trip delay. The value of 0xF chosen below adds extra margin but also impacts read-to-write turn-around performance. The value 0xC can be used in this field because CL=9 was programmed previously.

I believe the standard GEL program and the sample code provided as part of ProcSDK program this field to 0xF. It can be tuned to a lower setting based on your board design. You may be able to go as low as CL+2. I recommend that you use 0xF until after you have fully tested your implementation for robustness. Only thereafter do I recommend that you reduce this field to an optimized setting. Setting it too low will break the DDR interface.

Tom

0 Joakim Jarfjord over 6 years ago in reply to Tom Johnson 16214

TI__Expert 4710 points

Hi Tom,

Please have a look at the latest update from the customer and give us your comments.

Thanks and regards,

Joakim

From customer:

------------------------

Tom’s answer is not clear with conformance to JESD79-3C page 26 and Micron 4Gb_DDR3L.pdf in his reference to sprugv83.pdf page 32-33 and spabl2e.pdf page 10 (excerpts below). The equations RL=CL+AL and WL=CWL+AL was obtained from Micron 4Gb_DDR3L.pdf pages 161 and 172: "See attached file p161_p172.jpg"

Can we get better clarity here from Tom or someone else with respect to conformance to JESD79-3C DDR3, that is where or how is DDR PHY Control Register DDR_PHY_CTRL_1[4:0]=READ_LATENCY value mapped in DDR3 MR[3:0] Registers, we only see CL, CWL and AL and no RL entry. We need to have this clarified?

Will send some additional document references directly to you.

0 Tom Johnson 16214 over 6 years ago in reply to Joakim Jarfjord

TI__Mastermind 46460 points

Joakim,

From my reading of the JEDEC spec, it appears that use of the AL offset is an SDRAM feature that can be used by the Controller to present read and write commands with an offset. Since our Controller does not need this offset, the AL field in MMR1 is set to [00] to disable this feature. I do not see this as violating the JEDEC spec.

I have presented my conclusion to the DDR3 Controller design team for their comments.

Tom

0 Tom Johnson 16214 over 6 years ago in reply to Tom Johnson 16214

TI__Mastermind 46460 points

Joakim,

Below is the confirmation from the architect:

"AL is a feature, and our controller does not use it. AL will add more latency to the commands and degrades performance."

Tom

0 Tom Johnson 16214 over 6 years ago in reply to Tom Johnson 16214

TI__Mastermind 46460 points

Joakim,

I posted a request for a proper length matching report on the 18th. This is still needed to verify the PHY_CALC worksheet and it is also needed for calculating the optimal READ_LATENCY value.

Tom

0 Joakim Jarfjord over 6 years ago in reply to Tom Johnson 16214

TI__Expert 4710 points

Hi Tom,

Here is the latest reply from the customer:

Best regards,

Joakim

-----------------------

Thank you for the response. We are still compiling the length matching report for Tom to complete his review. We will provide this report as soon as possible.

We have noted the TI DDR3 architect’s response. We are now completely lost here. Increasing RL increases latency above CL, which has made significant improvement in our system as opposed to degrading performance. Are we missing something here?

We understand that JESD79-3C DDR3 AL possible specification setting are AL=0, CL-1 or CL-2. So AL=0 still conforms to JESD79-3C DDR3, but this is not an optimal setting and defeats use of options AL=CL-1, and CL-2. What we understood of AL was the improved system scheduling capability at the expense of speed (BW) to prevent “Data Gaps” which can impact our data sample collection in our system as shown below (from Micron attachment “TN4702.pdf” pp 15-16 DDR2 AL example, but applies to >=DDR2 ie DDR3).

What we still do not understand is the mapping of DDR_PHY_CTRL_1[4:0]=READ_LATENCY=RL=CL+AL. With this equation if CL is 10=0xA and RL is set to say 18=0x12 (Register Value 17=0x11), will the RL OFFSET CL-2=10-2=8 , be mapped to AL=CL-2 or this mapping is done somewhere else in DDR3, and AL is still set the default 0x00 value? We look forward to closing on this with you, with the input from the TI DDR3 Controller Design Team.

0 Tom Johnson 16214 over 6 years ago in reply to Joakim Jarfjord

TI__Mastermind 46460 points

Joakim,

I think I understand the confusion. You restated the below equation in your last post:

DDR_PHY_CTRL_1[4:0]=READ_LATENCY=RL=CL+AL

I think there is a semantics problem here. That is why you keep asking about AL and I do not understand why. In this context READ_LATENCY and RL are not the same term. The equation RL=CL+AL is a valid JEDEC equation discussing the number of clocks in a pipelined read access. It is not affected by write leveling delays.

The equation DDR_PHY_CTRL_1[4:0]=READ_LATENCY is a PHY delay term that defines the minimum number of clocks needed between a READ and a WRITE transaction to prevent data corruption. It must include the longest round trip delay which is dominated by the write leveling delay. This longest round trip delay (rounded up to the nearest number of clock periods) is then summed with the CL to obtain the proper DDR_PHY_CTRL_1[4:0] delay value.

Note that the Micron document excerpt in your previous post is about DDR2. Note that DDR2 and DDR3 are vastly different due to fly-by routing and the associated write leveling. Expected performance and configuration are also very different.

Tom

0 Joakim Jarfjord over 6 years ago in reply to Tom Johnson 16214

TI__Expert 4710 points

Hi Tom,

A follow up / closing question on the same topic from the customer:

Best regards,

Joakim

-------------------------------

We have one more final question we need resolved, now that we know that:

DDR_PHY_CTRL_1[4:0]= CL+ IO Delay +Board Delay-1

Our new current setting, with good performance, is:

CL=10
IO Delay+Board Delay=8

Therefore DDR_PHY_CTRL_1[4:0]= 10+8-1=10+7=17=0x11. This is okay with “Keystone Architecture DDR3 Memory Controller User's Guide” sprugv8e.pdf on page 80 (excerpt below) that allows max value of DDR_PHY_CTRL_1[4:0]=CL+7 ie CL+8-1 and min value of DDR_PHY_CTRL_1[4:0]=CL+1 ie CL+2-1. However in “KeyStone I DDR3 Initialization” sprabl2e.pdf on page 10 there is:

We need some clarity here as to the meaning of “conservative value for it is CL+3”. This seems to limit max value of DDR_PHY_CTRL_1[4:0] to DDR_PHY_CTRL_1[4:0]=CL+3 ie CL+4-1 ie IO Delay+Board Delay=4 and not 8. I understand we need to measure IO Delay+Board Delay but we need just need to know if the limits are 2 to 4 or 2 to 8 on of DDR_PHY_CTRL_1[4:0].

0 Tom Johnson 16214 over 6 years ago in reply to Joakim Jarfjord

TI__Mastermind 46460 points

Joakim,

I do not understand where they are getting an IO delay of 8. The unit here is clock periods. The upper limit on this delay is 4 clock periods. That is why CL + 3 is listed as a conservative answer.

Where are you getting the equation DDR_PHY_CTRL_1[4:0] = CL + IO Delay + Board Delay - 1?

Tom

0 Patrick Chimfwembe over 6 years ago in reply to Tom Johnson 16214

Prodigy 40 points

Hi Tom,

We understand DDR_PHY_CTRL_1[4:0] is in units of clock cycles (^tCLK). I will try and answer/clarify your questions as follows:

“where are they getting an IO delay of 8”? The DDR_PHY_CTRL_1[4:0] register has min setting of CL+1 and max CL+7, thus the question is, is an IO+Board Delay of 7+1=8 (^tCLK) possible (just checking the upper and lower limit of this) or this MUST be the conservative 3+1=4 max to get a of min CL+1 and max CL+3.

“Where are you getting the equation DDR_PHY_CTRL_1[4:0] = CL + IO Delay + Board Delay - 1?”

The equation comes from TI E2E on “Common DDR Issues:

http://processors.wiki.ti.com/index.php/Common_DDR_Issues

Excerpt:

The equation is DDR PHY=CL + IO delay + board delay, but programmed value into this register is less 1 (ie -1) from “The programmed value should always be programmed as the chosen value minus one” (highlighted in blue below)

All we are asking is what is the minimum and maximum value to be written into DDR_PHY_CTRL_1[4:0], is it CL+1/+7 or is the maximum value bounded by “KeyStone 1 DDR3 Initialization” sprab2le.pdf page with max CL+3.

Hopefully the above clarifies the initial first question reiterated above.

Kind regards,

Patrick

0 Tom Johnson 16214 over 6 years ago in reply to Patrick Chimfwembe

TI__Mastermind 46460 points

Patrick,

Why are you trying to get to 8 with the IO Delay + Board Delay? Please explain what you think each of these terms means.

I have previously explained that the upper limit to this is the maximum round trip delay (in clock cycles) for any data byte. This value cannot exceed 4 clock cycles per limitations in the PHY logic. I have actually never seen a customer layout where this has exceeded 3 clock periods and almost all are less than 2. Please refer to the detailed discussions in sections 6.3.1.9 and 6.3.1.10 of the DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1C) for more explanation on the associated delay calculations.

Therefore, per the register definition for READ_LATENCY = CL + value - 1, this value must be at least the number of clock periods required for the round-trip delay (rounded up to the nearest whole number). Since the PHY logic has an upper limit of 4 clocks for round-trip delay, this equation can be satisfied with the conservative solution READ_LATENCY = CL + 4 - 1. This is the equation provided in the KeyStone I DDR3 Initialization Application Report (SPRABL2E) at the bottom of page 10.

Tom

0 Patrick Chimfwembe over 6 years ago in reply to Tom Johnson 16214

Prodigy 40 points

Dear Tom,

I completely understand terms IO/Board delays relating to DSP/DDR3 round trip delay. I was trying to understand the definition in "KeyStone Architecture DDR3 Memory Controller: User's Guide" sprugv8e.pdf page 80 DDR_PHY_CTRL_1[4:0]=READ_LATENCY with "Maximum value possible = CAS latency +7" and "Minimum value possible = CAS latency +1", ie DDR_PHY_CTRL_1[4:0]=READ_LATENCY=CL+[1 to 7]. I understand the constraint, which I have been continually referencing, from "KeyStone I DDR3 Initialization" sprabl2e.pdf page 10 which gives constraint DDR_PHY_CTRL_1[4:0]=READ_LATENCY=CL+[1 to 3]. In the process of trying to understand why this has a lower upper limit, I noticed that this document is specific to KeyStone I DDR3. I think I now understand, this lower limit of DDR_PHY_CTRL_1[4:0]=READ_LATENCY=CL+[1 to 3] is for KeyStone I devices, whereas for Keystone II devices, this could be higher possibly with DDR_PHY_CTRL_1[4:0]=READ_LATENCY=CL+[1 to 6] from "DDR3 Design Requirements for KeyStone Devices" sprabi1c.pdf page 28 6.3.1.12 Round-Trip Delay Impact on Routing - KeyStone II versus page 26 Round-Trip Delay Impact on Routing - KeyStone I. I think we are now aligned and can close on this.

Thank you for your assistance and patience.

Kind regards,

Patrick

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