Other Parts Discussed in Thread: XIO2213B, TMDSEVM6678
Hello Champs,
Customer designed his own C6674 board, XIO2213B is connected to C6674 PCIe, below is the configuration code.
PCIE_Loopback_Mode loop_mode = PCIE_LOOPBACK_DISABLE;
PCIE_cfg.serdes_cfg.inputRefClock_MHz = 100;
PCIE_cfg.serdes_cfg.linkSpeed_GHz = 2.5;
PCIE_cfg.serdes_cfg.numLanes= 1;
In the link training, the code is stuck in the gpPCIE_CAP_implement_regs->DEBUG0[4:0] DETECT_QUIET status.
BTW, he tested the phy_loopback mode is correct, the link training works.
Thanks.
Rgds
Shine
