• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 103 subscribers
  • Views 430 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6454: clk0

yair adelstein
Prodigy 40 points
Part Number: TMS320C6454

For more then 15 years we use same design same code

 

We are using tms320c6454  dsp  in   McBSP

 

We use  Dx0 as data output

                Clk0 as sync clock output

                Clkr0 as output gpio

                Fsro   as input gpio

                Dr0    as output gpio

 

                While  clk0 is enable  data is going out synchronized .

 

                Lately in some boards  ,  from 1 to 6 power up , clock is not appear at Clk0  while data goes out from Dx0

                The input clock to the Clock and Frame Generation , at pin Clks is stable .

                When this occurs , only power down , and power up , solve the issue .

 

                Did you saw such issue in the past ?

 

                Thanks a lot

 

  • 0
    TI__Guru 65405 points
    Hi Yair Adelstein,


    The observed board behavior is unexpected. I'll contact with hardware experts and will back later.

    Regards,
    Tsvetolin Shulev
  • 0 in reply to yair adelstein
    Prodigy 40 points
    I found that in other card clock appear at Clk0 while data goes out from Dx0 ' and it stuck in middle .
    Could it that reset sequence , not met spec , can cause such strange behavior ?
  • 0 in reply to yair adelstein
    TI__Guru 65405 points
    Due to the US holiday the responses may be delayed until the week of November 26th.

    Regards,
    Tsvetolin Shulev
  • 0
    TI__Guru*** 125430 points

    yair adelstein said:

    We use  Dx0 as data output

                    Clk0 as sync clock output

    By Clk0, are you referring to CLKX0 (Ping AG6)?

    yair adelstein said:

                    Clkr0 as output gpio

                    Fsro   as input gpio

                    Dr0    as output gpio

    Are you saying you've configured these as GPIO through the PCR[RIOEN] field?  DR0 is an input-only pin, so I don't understand your comment there either.

    yair adelstein said:
       The input clock to the Clock and Frame Generation , at pin Clks is stable .

    So the CLKS pin (AJ4) is also being used?  I need to be clear on the basic setup.  Is this accurate:

    • Bidirectional data flow, i.e. using both DX and DR
    • CLKX and CLKR are generated by c6454, and are derived from the CLKS pin
    • FSX and FSR  are generated by external device

    What frequency are each of these pins?

    yair adelstein said:
    When this occurs , only power down , and power up , solve the issue .

    Just so I'm clear, are you saying that asserting the reset pin is not sufficient to clear this condition? Only power cycling will fix it?

    yair adelstein said:

    Did you saw such issue in the past ?

    I don't recognize this issue.  We'll need to dig in further to better understand what's happening.

    Please provide the following registers for a "good" case and "bad" case:

    • PERCFG0 - 0x02AC 0008
    • PERSTAT0 - 0x02AC 0014
    • SPCR0 - 0x028C 0008
    • RCR0 - 0x028C 000C
    • XCR0 - 0x028C 0010
    • SRGR0 - 0x028C 0014
    • MCR0 - 0x028C 0018
    • PCR0 - 0x028C 0024

    Best regards,
    Brad

  • 0 in reply to Brad Griffis
    Prodigy 40 points
    Dr0 is input my mistake

    By Clk0, are you referring to CLKX0 (Ping AG6)? yes

    CLKS pin (AJ4) yes input 40 mhz

    FSX and FSR are generated by external device ? , No are used as io , fsr0 input fsx0 not used .

    all io pins are discrete lines dc .

    clk0 is 50 mhz

    dx0 output of data at 50 mhz

    clkr0 output pin

    only power down and up solve the issue . yes