For more then 15 years we use same design same code
We are using tms320c6454 dsp in McBSP
We use Dx0 as data output
Clk0 as sync clock output
Clkr0 as output gpio
Fsro as input gpio
Dr0 as output gpio
While clk0 is enable data is going out synchronized .
Lately in some boards , from 1 to 6 power up , clock is not appear at Clk0 while data goes out from Dx0
The input clock to the Clock and Frame Generation , at pin Clks is stable .
When this occurs , only power down , and power up , solve the issue .
Did you saw such issue in the past ?
Thanks a lot