CCS/TMS320C6674: How to use core1 control PCIE?

user4033547

Part Number: TMS320C6674

Tool/software: Code Composer Studio

We have a C6674 DSP and a FPGA (Cyclone IV) with PCIE hard ip core on board. When we use CORE0 to access the PCIE with SYS/BIOS, everything is ok, we can use DMA in FPGA to transmit data through PCIE. If we use CORE1 to do the work, we can see the PCIE trainning and configuration is ok, however, CORE1 cannot receive the MSI interrupt.

In PCIE_Interrupts_Init(), i made same change: (changing the event num from 33 to 44)

void PCIE_Interrupts_Init(void)
{
/* Disable Global host interrupts. */
gpCIC0_regs->GLOBAL_ENABLE_HINT_REG= 0;

uiPCIE_pend_host_event_num= 44; //33

/*map PCIE Interrupt events to CIC0 out33*/
KeyStone_CIC_event_map(gpCIC0_regs, CSL_INTC0_PCIEXPRESS_ERR_INT, 44);//33
KeyStone_CIC_event_map(gpCIC0_regs, CSL_INTC0_PCIEXPRESS_PM_INT, 44);//33

/* Enable the host interrupt */
//squwal added
gpCIC0_regs->HINT_ENABLE_SET_INDEX_REG = uiPCIE_pend_host_event_num;

/* Enable Global host interrupts. */
gpCIC0_regs->GLOBAL_ENABLE_HINT_REG= 1;

//clear all interrupt status registers of PCIE
KeyStone_PCIE_clear_interrupts();

/*on Nyquist, CIC0 out64 event number are 22 on core 0; on Shannon,
CIC0 out33 event number are 22 on core0. Map this event 22 to INT5.
Map PCIE MSI event to INT4*/
//CIC0 out44 event number are 22 on core1.
gpCGEM_regs->INTMUX1 = (22<<CSL_CGEM_INTMUX1_INTSEL5_SHIFT)
|(CSL_GEM_PCIEXPRESS_MSI_INTN<<CSL_CGEM_INTMUX1_INTSEL4_SHIFT);

//enable INT4 and INT5
CPU_interrupt_enable((1<<4)|(1<<5));
}

And in HWI, i change the Event ID from 33 to 44. And what else should i do? Is there anyting need to do in FPGA? Any suggestion is appreciated.

over 5 years ago

0 Victor Kazmirenko over 5 years ago

Guru 13162 points

Hello!
One notable difference is that Core0 receives PCIExpress_MSI_INT0, while Core1 receives PCIExpress_MSI_INT1. Thus, FPGA must request different MSI Vector number to reach Core1.

There might be a typo in data manual similar to C6670. The latter could receive all 32 MSI's, 8 per core. So probably yours could receive more that 1 MSI per core as well.

0 user4033547 over 5 years ago in reply to Victor Kazmirenko

Prodigy 50 points

Thank you for your reply! Now i think the code below is to allocate msi interrupt vetor:

KeyStone_PCIE_RC_MSI_allocate((PCIE_MSI_Regs *)&gpPCIE_remote_EP_regs->MSI_CAP,
PCIE_RC_BAR0_ADDRESS+((Uint32)&gpPCIE_app_regs->MSI_IRQ)-(Uint32)gpPCIE_app_regs);

and i changed the last code in it:

//write the index of the first MSI allocation for the EP
msi_regs->MSI_DATA= uiMSI_index+1;

now i can get msi interrupt in CORE1, however , i wonder whether there is any "offical" or more correct method to do it?

0 Victor Kazmirenko over 5 years ago in reply to user4033547

Guru 13162 points

Hello!

I am terribly sorry to tell I could not recognize pieces of code you're providing. I can't tell, why the line you've shown did help.

Nevertheless, MSI operation is pretty simple to understand. Consider the case where EP makes MSI to RC. During configuration RC tells EP address of it register, where it is going to receive MSI's. One may think that is just address of memory mapped register, and hardware around it detects write accesses. So when EP makes write transaction to RC, and that word falls onto specified address, RC hardware will recognize write access as MSI. Next, write access with single dword of payload may carry more information, that just write access. So value written to that MSI_IRQ register is recognized as interrupt vector, i.e. writing 1 is recognized as MSI1, 23 as MSI23. Number of MSI vectors available depends on your device and can be further reduced. Moreover, in you DSP program you may write ti MSI_IQR register a value, and that value will trigger appropriate MSI.

Now closer to our topic. When your FPGA is making interrupt to DSP as RC, it looks into MSI address register to compose address of write packed, but it also makes payload. And that payload is what really makes different vectors. So it is responsibility of FPGA to send 0 as payload to make MSI0 reaching Core0 and send 1 to make MSI1 reaching Core1.
I am not familiar with Altera FPGAs, I'm from Xilinx world. Here we also have IP block for PCIe, and MSI function particularly. That IP block has di bus input, which communicates value of MSI vector (effectively transferred as payload) and rec/ack handshake signals. Thus in my FPGA design I have MSI controller, which has multiple interrupt input lines and priority encoder to convert active request line into binary number, this number is presented to PCIe IP and request signal is then triggered. This is it.

Finally, if we refer SPRUGS6D KeyStone Architecture Peripheral Component Interconnect Express (PCIe) User Guide, clause 2.14.1 Interrupt Allocation, it tells that MSIs are actually multiplexed. Core0 can receive as MSI0, so MSI8, 16, 24. So one may send 0, 8, 16, 24 as payload of MSI request packet, and they all will reach Core0.

Hope this helps.

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CCS/TMS320C6674: How to use core1 control PCIE?