Other Parts Discussed in Thread: OMAPL138
Hi, dear TI processor forum.
I am currently using an OAMP-L137 in an embedded application, and we started developing a simple PRU program to access some registers on an external FPGA in real-time.
I have found little to no mention in the documentation about the timing access of the PRU to the external memory:
- the PRU wiki states for the LOAD/STORE instructions 1 (or 2) + word count CPU cycle, so it seems the PRU can't handle slow external memories, with a read access timing of 4 or more PRU cycles
- is this correct?
- or is the PRU using the same timing of the ARM core?
Best regards
Michele