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Part Number: TDA2EXEVM
Hello,
The SPI chip select setup time(Time since CS goes low to SPI clock) is measured to be around 8.7 micro seconds.
But as per the TCAN4550 manual (tcss) value can be as minimum as 25ns.
Query 1: How this time can be minimized?
Query 2: Is this configurable using parameter SpiTimeClk2Cs? (As checked in Ebtresos tool for plugins as per delivery mcal_setupwin32_01.09.00.30, this cannot be configured, please find the attached snapshot of tresos window)
Thanks
Hi Amar,
On TDA2EX, the "SpiTimeClk2Cs" cannot be used to specify the CS delay. As CS delay is expressed in terms of SPI bus clock by the hardware and not absolute time period.
Please use "SpiCsIdleTime" instead.
Value of SPI_DATADELAY_0 configures for 0.5 clock pulse delay between activation of CS and data.
Value of SPI_DATADELAY_1 configures for 1.5 clock pulse delay between activation of CS and data, SPI_DATADELAY_2 for 2.5 and so on.
In this particular case, please increase the SPI clock to maximum and set SpiCsIdleTime to SPI_DATADELAY_0. This will ensure the delay between and Data is 0.025 micro-seconds (for 20 MHz SPI bus clock)
Regards, Sujith
Hi Amar,
Can we close this thread? Would you have any follow up questions?
Regards, Sujith