TMS320VC5402: TMS320VC5402 : ”Standard serial port boot” issue

Hi Michi,

From 2.2.4 in SPRA618B:
"The bootloader also sets the XF pin low to indicate that the serial port is ready to receive data. The DSP then polls the IFR to determine which serial port has data input (BRINT0, or BRINT2). When the desired serial port has been identified, the bootloader continues to read the same port to load the entire boot table."

My understanding is that the bootloader expects the host processor to monitor XF and wait until it goes low before driving the McBSP BCLKR and BFSR signals.

But I don't expect much issue if the clocks are driven before XF goes low as long as the data is not transmitted until after XF goes low. But I wonder if there could be a synchronization issue if XF goes low in the middle of a McBSP frame. This might prevent the valid keyword from being received by the McBSP, leading it to move to the IO boot then HPI boot before re-attempting to boot from McBSP. There appears to be on indication when the Standard Serial Port Boot is re-attempted, but the application could use a GPIO or some signal to inform the host processor that the DSP has booted after completing the transfer.

The McBSP software initialization has a requirement to wait for two bit clocks before releasing XRST and/or RRST to enable the serial port. This is to ensure proper synchronization internally. I cannot confirm with the bootloader source code if this requirement is satisfied, but I assume the bootloader waits some time after XF before releasing RRST to satisfy this requirement... It should then latch the first word based on the BFSR changing state.

Further restrictions:
The serial port receive clock (BCLKR) is supplied externally and cannot exceed half the frequency of the C5402 CPU clock.

A minimum delay time of 40 CPU clocks should be provided between the transmission of each word. This can be achieved by either slowing the receive clock frequency, or providing additional clocks between transmitted words.

Regards,
Mark