RTOS/AM3352: Delay control between MMC0_CLK and MMC_CMD/DAT for MMC/SD module

The insertion delay of SN74CBT3244C should be minimum. However, we always recommend timing margins for all peripheral interfaces are verified by performing timing analysis that includes all contributions to signal delay. This includes delays introduced by external components and PCB signal traces.

The data sheet of each device specifies a setup and hold time parameter, which defines the period of time where the signal must be valid for synchronous inputs (CMD and DAT) relative to a specific edge of CLK. The signal must be at a valid logic level before the specified setup time and remain at the same valid logic level until after the specified hold time. The product designer needs to consider the worst case output delays of the attached device and delays inserted by external components and PCB signal traces to confirm timing margin for each of these parameters at the pins of the respective device.

The only delay control provided on AM335x is via the SD_HCTL[2] HSPE bit. AM35x will transition CMD and DAT signals on the falling edge of CLK when this bit is cleared to 0, and rising edge of CLK when this bit is set to 1.

Regards,

Paul