Hi,
In the past we used DM8168 Speed Grade 0. Setup works fine for us.
Settings in u-boot:
ARM clk: 930 MHz
DDR clk: 796 MHz
HDVICP clk: 504 MHz
L3 Fast clk: 465 MHz
HDVPSS clk: 232 MHz
Ducati M3 clk: 232 MHz
DSP clk: 756 MHz
Settings in link_api/system common.h:
#define SYSTEM_M3VPSS_FREQ (232*1000*1000)
#define SYSTEM_M3VIDEO_FREQ (232*1000*1000)
#define SYSTEM_DSP_FREQ (756*1000*1000)
Now we try to use DM8168 Speed Grade 4
Settings in u-boot:
ARM clk: 1209 MHz
DDR clk: 796 MHz
HDVICP clk: 636 MHz
L3 Fast clk: 576 MHz
HDVPSS clk: 288 MHz
Ducati M3 clk: 288 MHz
DSP clk: 1008 MHz
My question is:
What are the maximal values for M3 clocks in this case?
#define SYSTEM_M3VPSS_FREQ ( ? * 1000*1000)
#define SYSTEM_M3VIDEO_FREQ ( ? * 1000*1000)
#define SYSTEM_DSP_FREQ ( ? * 1000*1000)
