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Original question:

AM5718: DDR memory multiple speed grades

AM5718: Supported DDR3 speed grades

David Olson61
Intellectual 350 points
Part Number: AM5718

The SoC we are using is AM5718, hence have been referring to the data sheet with the name "SPRS957G –MARCH 2016–REVISED MAY 2018".  Table 6-15 in that document states that EMIF_DLL_FCLK max frequency is 266 MHz.  This corresponds to DDR3-1066.

The U-Boot code base is TI's distribution, branch ti2017.04-rc1.  The board file on which we based our own board file, board/ti/am57xx/board.c contains code to set up PRCM based on the processor model, choosing either a "DRA72X" or "DRA7XX" configuration.  For the purposes of that test, our processor type, as determined by the code reading version registers, is DRA722-GP ES2.0 so the code chooses the "DRA72X" configuration.  The only difference between those two configurations is in the setup of the DDR DPLL.  While the DRA7XX setup is for DDR-1066 (EMIF_DLL_FCLK = 266 MHz), the DRA72X setup is for DDR-1333 (EMIF_DLL_FCLK = 333 MHz).

So I have a TI data sheet telling me in effect that the highest supported speed grade is DDR-1066 but TI code choosing the higher speed grade DDR-1333.  So is this a mistake in the data sheet, a bug in the code, or confusion on my part?

  • 0
    Intellectual 350 points
    I found the commit which added support for DDR-1333. It is c7e57698256d84dd0872a705daba457b5dadcc42. The commit title is "board: ti: am571x: Add 666MHz support for AM571x IDK" and the body of the commit message says, in part "AM571x supports DDR running at 666MHz."

    (There's lots of clocks related to DDR access so there's lots of ways to refer to the DDR speed. Unless I'm totally confused, "DDR running at 666MHz" requires EMIF_DLL_FCLK to be 333 Mhz which the data sheet says is beyond the max allowed.)
  • 0 in reply to David Olson61
    TI__Guru**** 393215 points
    Hi,

    Please see section 8.2.2.5 in the AM571x Datasheet Rev. G. EMIF_DLL_FCLK is a common functional clock for all DLLs associated with the EMIF
    PHYs.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 350 points

    Section 8.2.2.5 definitely states that DDR3-1333 is supported.  But as I understand things, there is an apparent inconsistency in that document.  Here's my reasoning:

    • DDR3-1333 means a DDR clock rate of 667 MHz
    • Referring to AM571x TRM (SPRUHZ7H), DPLL_DDR provides two clocks to EMIF: EMIF_PHY_GCLK and EMIF_DLL_GCLK (TRM Figure 3-55).
    • EMIF_PHY_GCLK is the source of EMIF_PHY_FCLK which, according to TRM Table 15-95, "is equal to the DDR3 clock rate", i.e. 667 MHz.
    • EMIF_DLL_GCKL is the source of EMIF_DLL_FCLK according to TRM Table 15-95.  I wasn't able to find anything stating how to set that clock however the TI code sets it to 1/2 of the DDR clock rate, i.e. 333 MHz.
    • Returning to the data sheet, Table 5-10 (Maximum Supported Frequency) contains an entry for EMIF_DLL_FCLK which references Table 6-15.
    • Table 6-15 clearly states that EMIF_DLL_FCLK max frequency is 266 MHz.

    So as I understand your reply, I can rely on section 8.2.2.5 of the data sheet and run DDR3-1333 with EMIF_DLL_FCLK = 333 MHz and can ignore Table 6-15 in that same data sheet that says I cannot run that fast?

  • 0 in reply to David Olson61
    TI__Guru* 80880 points

    Hi David, EMIF_DLL_FCLK should stay its max of 266MHz.    If you look at Figure 3-55 in the TRM, you will see that EMIF_DLL_GCLK source is from CLKOUTX2_H11.  H11 is a post divider off the DDR PLL.  Go back to Figure 3-45 to see the PLL block diagram and the output from H11 post divider

    If you look at the formulas under Fig 3-45, you can derive EMIF_DLL_GCLK as (Fref * 2 * M / (N+1))/H11.  For both DDR3-1066 and DDR-1333 options, H11=8, as shown in the code below from u-boot, and the result of the formula is 266MHz for both cases as well.

    static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {

    {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz   */

    {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz   */

    {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

    {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

    {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz   */

    {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz   */

    {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */

    };

    static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {

    {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz   */

    {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz   */

    {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

    {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

    {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz   */

    {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz   */

    {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */

    };

    Regards,

    James

  • 0 in reply to JJD
    Intellectual 350 points

    I'm afraid I'm still confused.

    The equation for EMIF_DLL_GLCK depends on Fref, M, N, and H11.  For the two cases, Fref, N, and H11 are the same values of, respectively 20 MHz, 4, and 8.  However M is either 333 or 266.  Therefore EMIF_DLL_GCLK must differ between those two cases.  If I rewrite that equation, substituting in values that are constant between the two cases, I get

    EMIF_DLL_GCLK = (20 x 2 x M / (4 +1)) / 8 = M

    Further, there's this cool tool, TI_Clock_Tree_Tool written in Java that I downloaded from the TI website.  This shows the whole clock system and allows one to click on various objects in the diagram, fill in the parameters, and see the results on the diagram as well as the bit patterns in the controlling registers.  Using that tool and filling in Fref, M, N, and H11, I also see EMIF_DLL_GLCK set to either 333 MHz or 266 MHz depending on the value of M.

    Can you help me see the error in my logic?

  • 0 in reply to David Olson61
    TI__Guru* 80880 points
    David, sorry, my mistake. I believe you are correct. Let me double check this internally here, as there seems to be several typos across data manual and TRM related this.

    Regards,
    James
  • 0 in reply to JJD
    TI__Guru* 80880 points
    David, we are in the process of correcting the datasheet. Next revision will have the fix to adjust max EMIF_DLL_FCLK = 333 MHz for the AM57x device which support DDR3-1333.

    Regards,
    James
  • 0 in reply to JJD
    Intellectual 350 points
    Thanks so much for chasing this down. I've always been a stickler for complying with specs so it's good to know that this was just a missed documentation update.
  • 0 in reply to David Olson61
    TI__Guru* 80880 points
    Yes, the devil is always in the details. Thanks for your persistence.

    Regards,
    James