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Original question:

AM3351: [am335x] are resistors compulsory for SYSBOOT signals?

AM3352: SYSBOOT[9] default state

Tony Tang
Mastermind 27962 points
Part Number: AM3352

My customer want to use ROM ECC NAND boot, but forgot to pull down SYSBOOT[9], left it un-pulled/floating, but it still can boot from NAND, did not find issue so far, and measured on SYSBOOT[9] is LOW, want to make sure whether it is internal pulled down in default, as this product deployed in field already, and volume is big, fell upset about the stability, so want to ask for confirmation.

  • 0
    TI__Guru*** 125430 points
    Tony,

    SYSBOOT[9] is high-Z as listed in the data manual. The scope itself may have a very small resistance to ground, so the act of measuring this signal might be changing its value.

    Instead of trying to probe the pin, a more reliable method of knowing what is actually latched would be to read the control_status register at address 0x44e10040. Bit 17 of this register will show the state of SYSBOOT[9]. This is what the ROM code looks at to determine its behavior. The customer would need to examine this bit across a sampling of boards in order to get a better understanding of their exposure. It's not clear to me if their lack of issues relates to the pin being sampled in the desired state (low) or if they have been fortunate not to have any catastrophic NAND errors.

    Best regards,
    Brad
  • 0 in reply to Brad Griffis
    TI__Mastermind 27962 points

    Brad,

    I read it on EVM, removed pull up / pull down resistor on SYSBOOT[9], it is 0 as below snapshot. I am curious what is the value when latch Hi-z status pin?

  • 0 in reply to Tony Tang
    TI__Mastermind 27962 points
    Brad,
    would you please help confirm.
  • 0 in reply to Tony Tang
    TI__Guru*** 125430 points

    Tony Tang said:

    Brad,

    I read it on EVM, removed pull up / pull down resistor on SYSBOOT[9], it is 0 as below snapshot. I am curious what is the value when latch Hi-z status pin?

    Tony,

    Sorry, I was on vacation last week.  The value in this control register is latched when reset is released, i.e. it never changes.

  • 0 in reply to Brad Griffis
    TI__Mastermind 27962 points

    Brad,

    I mean when left sysboot[9] floating,  read from Control_status register, this bit is 0. I know the it won't change after latched. My question are:

    #1. When left sysboot[9] floating, what is its status latched into control register when reset signal released?

    #2. As you said in previous reply, it is Hi-z. but what is Hi-z status?

    #3. Now I read it from control register is 0, is it reliable? or will sometimes it maybe 1?

  • 0 in reply to Tony Tang
    TI__Guru*** 125430 points

    Tony Tang said:
    #1. When left sysboot[9] floating, what is its status latched into control register when reset signal released?

    The status is reflected in bit 17 of the register.

    Tony Tang said:
    #2. As you said in previous reply, it is Hi-z. but what is Hi-z status?

    It would be influenced by process, e.g. the transistor switching threshold will not be precisely the same on every device.  It will also be highly susceptible to environmental noise, etc.

    Tony Tang said:
    #3. Now I read it from control register is 0, is it reliable? or will sometimes it maybe 1?

    I don't have the info to tell you.  The proper design of course is to have a pullup or pulldown on the pin.  You or the customer would need to perform your own testing to better understand the behavior in this scenario.