AM3352: SYSBOOT internal circuit

Hi Kanae-san,

Can you provide the following details:

• What specifically is failing?
• How the customer is detecting this failure?
• What are the customer's sysboot settings?

Regards,

Melissa

One other important data point in this discussion will be the value of the control_status register (address 0x44E10040).  Bit 17 of that register represents the value latched from sysboot[9] when reset was released.  This register value is what is used by the boot ROM, i.e. it is the thing that really matters when it comes to issues with boot modes.

Hi Melissa and Brad,

Thank you for your replies!

Here are the details.

What specifically is failing?
>>>Regarding to sysboot [9], NAND ECC setting must be set Pull-Down connection.
However it is set Pul-Up connection that is setting as ECC processing on NAND side.
Customer uses "Raw NAND without ECC function", therefore,
the system does not start when the bit corruptions occur in the program area,

How the customer is detecting this failure?
>>> For finding the solution to avoid the error tentatively,
if the PU resistance is removed and the system can start
at "indeterminate state" in Low state.
Customer is verifing the corroborative evidence that is not in High state.
He confirmed with sample(N=30+α) that all results are the same.
Please refer to "SYSBOOT[9] open (now)" in the attached file.

waveform_image.pdf

What are the customer's sysboot settings?
>>>sysboot [9] is undefined state (both PU/PD not connected).

===
Default：　NAND boot 　
                 *It can boot from SD(MMC) and Eth(EMAC) via external key.
CLK OUT：　No
PHY MODE： MII
ECC：　NAND
XTAL：　26MHz

SYSBOOT[15-0]

Boot[0]：　 1
Boot[1]：　 1
Boot[2]：　 0
Boot[3]：　 0
Boot[4]：　 1
Boot[5]：　 0
Boot[6]：　 0
Boot[7]：　 0
Boot[8]：　 0
Boot[9]：　 1 ==> 0
Boot[10]：　0
Boot[11]：　0
Boot[12]：　0
Boot[13]：　0
Boot[14]：　1
Boot[15]：　1
===

--------------------------------------------------
My customer has already checked the control_status register,
and he knows the status is High or Low.
He needs to know why the SYSBOOT[9] can be Low state
at indefinite state and it can be the solution for keeping "Low state".

He has to explain the corroborative evidence to the end customer,
and he would like to have the internal circuit of SYSBOOT[9].

Here is another request.
In data sheet, Leakage current(Ioz) is only Max. 18uA and Min. and typ. values are blank.
Can you provide any information the reason why it is only Max. value?

Best regards,
Kanae

Hi Melissa and Brad,

Could you provide the internal circuit of SYSBOOT[9] pin and
the reason why it is only Max. value of Leakage current(Ioz) in datasheet?

This request does not require a warranty about TI devices.

My customer's ideal is to provide information to explain
the following to the end user:

・ SYSBOOT [9] is not be High.

If TI cannot provide these information,
I will explain to my customer that
he should be set pull-down to SYSBOOT[9]
if SYSBOOT[9] on their system need to be LOW.
There is no other way to explain that it is LOW.

Is the above explanation no problems?

If you need more information for this, please let me know.

Best regards,
Kanae

Hi Brad,

Thank you for your reply.

I can understand what you explain.

Best regards,
Kanae