AM3352: PCLK Jitter

Kz777

Part Number: AM3352

Hi Champs,

We used to connect AM3352 and Series device. And we turned out Series phase lock have removed due to AM3352 Jitter.

We set PCL 5.7MHz (Ts =175.6ns). When we measure this Ts at each of clock. Ts value shift to 174.9ns.

During each 500 clock, this value behave 175.6 to 174.9ns. When this Ts value less 175, it recover to 175.6ns after 250 clock.

It continue this jitter behavior like a frequency. Then, when the value less than 175ns, Series phase lock some times removed.

Do you have any idea to avoid such a phenomenon ? Or is it some expected behavior at PCLK HW ?

When you assign some Engineer, I will send customer detail data.

Regards,

Kaz

over 4 years ago

0 Biser Gatchev-XID over 4 years ago

TI__Guru**** 393215 points

Hi Kaz,

First thing to check is if you have not enabled Spread Spectrum Clocking by mistake in the Display PLL. This is register CM_CLKMODE_DPLL_DISP bit 12 (DPLL_SSC_EN). See sections 8.1.12.2.39 and 8.1.6.6 in the AM335x TRM Rev. P for details.

0 Kz777 over 4 years ago in reply to Biser Gatchev-XID

TI__Expert 7895 points

Hi Biser,

I have just checked this register. However, this register was disable statement.

I will send this detail customer document to you. And Please forward it PCLK HW engineer too.

Regards,

Kaz

0 melissaw over 4 years ago in reply to Kz777

TI__Genius 15200 points

Hi Kaz,

Can you confirm whether the customer's PLL settings match those defined in the TI SDK or AM335x gel files in CCS?

Regards,

Melissa

0 melissaw over 4 years ago in reply to melissaw

TI__Genius 15200 points

Kaz,

Can the customer also check the PLL power supply (VDDS_PLL_CORE_LCD) for stable voltage?

Regards,

Melissa

0 Kz777 over 4 years ago in reply to melissaw

TI__Expert 7895 points

Hi Melissa,

Actually, we confirmed this phenomenon on the TI GP EVM and reference software.

So, does this phenomenon expect behavior on the design ?

>Can the customer also check the PLL power supply (VDDS_PLL_CORE_LCD) for stable voltage?

- Actually, we confirmed same issue on the TI GP EVM and reference software also.

>Can you confirm whether the customer's PLL settings match those defined in the TI SDK or AM335x gel files in CCS?

-If we submit register map , can we review it ? Could you please tell us detail PLL register name ?

0 melissaw over 4 years ago in reply to Kz777

TI__Genius 15200 points

Hi Kaz,

The PLL registers of interest are:

CM_CLKMODE_DPLL_DISP
CM_CLKSEL_DPLL_DISP
CM_DIV_M2_DPLL_DISP

Also, what oscillator frequency is the customer using? Which reference software was used?

Regards,

Melissa

0 Kz777 over 4 years ago in reply to melissaw

TI__Expert 7895 points

Hi Melissa,

Thanks for reply.

Here is register value.

Register name Address Value
CM_CLKMODE_DPLL_DISP 0x44E00498 0x00000007
CM_CLKSEL_DPLL_DISP 0x44E00454 0x00003977
CM_DIV_M2_DPLL_DISP 0x44E004A4 0x00000201

>Also, what oscillator frequency is the customer using?

-24Mhz

>Which reference software was used?

-We confirmed it "Starterware" raster.c,h sample code.

Regads,

Kz777

0 melissaw over 4 years ago in reply to Kz777

TI__Genius 15200 points

Hi Kaz,

Given the customer's required PCLK frequency (5.7MHz) and oscillator frequency, a better DISP DPLL configuration would be N = 0, M = 19, and M2 = 1. Below are the corresponding register settings. Within the LCD module, they would also need to set CLKDIV = 80.

Register name Address Value

CM_CLKSEL_DPLL_DISP 0x44E00454 0x00001300
CM_DIV_M2_DPLL_DISP 0x44E004A4 0x00000201

Regards,

Melissa

0 Kz777 over 4 years ago in reply to melissaw

TI__Expert 7895 points

Hi Melissa,

Thank you for information.

Our customer is checking this apply.

So, I would like to make sure two thing.

1) When we apply this setting , does it affect to another peripheral clock parameter ?

2) Could you please give us what is advantage with this new setting ?

Regards,

Kz777

0 Kz777 over 4 years ago in reply to Kz777

TI__Expert 7895 points

Hi Melissa,

Regarding this effort, We are waiting customer feed back. So, Could you please also follow above two (1), (2) questions ?

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AM3352: PCLK Jitter