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DDR2/mDDR Layout

Amer Abufadel5389
Intellectual 460 points

Greetings,

  While following the traces between the DM355 and the DDR memory on my evalulation kit, I realized that the trace connecting DDR_DQGATE0 and DDR_DQGATE1 has does back and forth multiple times.  However, on pages 3 and 4 in SPRAAR3 Application report, it mentions that is should be routed like the data lines and back.  Can someone explain this please?  And why is the distance between the DM355 and DDR is what it is and not as close as possible on par to what is recommended?  I would have placed them much closer together, but I am not an expert so I may be missing a thing or two.  Any clarification is greatly appreciated.

 

Thank you,

 

A

  • 0
    TI__Mastermind 41665 points

    First I would like to say that the DM355 EVM is not really considered a reference design, most EVM boards are laid out very early on in the device's lifecycle, meaning not necessarily all of the collateral that is seen today was available when the EVM was designed, additionally EVMs are generally designed quickly, where the object is to get something that works out as fast as possible, thus the design is not necessarily the most optimal implementation possible. This is usually the reason for quirks found in the EVM design that one may not expect based on the device's documentation.

    Amer Abufadel said:
    While following the traces between the DM355 and the DDR memory on my evalulation kit, I realized that the trace connecting DDR_DQGATE0 and DDR_DQGATE1 has does back and forth multiple times.  However, on pages 3 and 4 in SPRAAR3 Application report, it mentions that is should be routed like the data lines and back.  Can someone explain this please?

    Looking at the DM355 EVM gerber files it seems that the rest of the DDR data lines are also being run back and fourth to meet length matching requirements, I have not done any formal measurements, but it looks like the length of the DQGATE0 to DQGATE1 trace is approximately 2x that of one of the data lines when the S curves on the data lines are taken into account as expected by the SPRAAR3 document. It does have to be routed so that the round trip from DQGATE0 to DQGATE1 appears electrically like the round trip of a data signal, however I do not believe it actually has to go under the DDR package itself to be effective, so what it has on the EVM gerber seems reasonable to me.

    Amer Abufadel said:
    And why is the distance between the DM355 and DDR is what it is and not as close as possible on par to what is recommended?  I would have placed them much closer together, but I am not an expert so I may be missing a thing or two. 

    I am not sure if there were other concerns regarding this with the EVM design, however it is possible that it was just laid out this way to be done faster/easier than a closer more optimal design, as mentioned above please keep in mind that the EVM is not a true reference design, the layout is not necessarily optimal.