AM5728: PCIe clock requirements

Lawrence Wong

Part Number: AM5728

Could you provide me with the PCIe Gen 1/ Gen 2 Clock Requirement for the AM57x (ex, V_CM, Jitter, etc) ?

Reviewed PCIE Base Specification Revision 2.0; however, I could not find the clock requirement.

Looking for confirmation that on AM57x side is okay no termination/AC caps at LJCB_REFN/P for LP-HCSL ? Since the reference schematic has LVDS output format which has AC caps and 100-ohm termination.

Requesting confirmation whether there is register configuration to identify the output clock mode either LVDS or LP-HCSL ?

over 5 years ago

0 -DK- over 5 years ago

TI__Mastermind 27890 points

Hello,

The clock requirements are outlined in section 4.3.3.5 of the Base Spec.

If using a HCSL clock source, no external caps are required on PCIe REFCLK.

If using a LVDS clock source, external caps are required on the PCIe REFCLK.

No register configuration is needed for these options.

0 Lawrence Wong over 5 years ago in reply to -DK-

TI__Genius 15000 points

Customer do not see PICe REFCLK requirement for PCIe GEN 2 in section 4.3.3.5 of the PCIe Base Spec. Could you verify which section of the spec shows PCIe REFCLK requirement for Gen 2 ?

Could review the attached PCIe REFCLK measurement to AM57x ? Customer design has LP-HCSL (Low Power HCSL) clock output format to AM57x

0 Tom Johnson 16214 over 5 years ago in reply to Lawrence Wong

TI__Mastermind 46460 points

Lawrence,

With the LP-HCSL clock input, are you following the HCSL input guidance (DC-coupled) or LVDS input guidance (AC-coupled)? The Data Manual only states that we accept HCSL or LVDS compliant clock signals. LP-HCSL in not listed as a supported option.

Tom

0 Tom Johnson 16214 over 5 years ago in reply to Tom Johnson 16214

TI__Mastermind 46460 points

Lawrence,

The following E2E is from another customer trying to use LP_HCSL:

https://e2e.ti.com/support/processors/f/791/t/637820

The E2E at the link below discussed options for using AC-coupled implementations:

https://e2e.ti.com/support/processors/f/791/t/686296

Tom

0 Tom Johnson 16214 over 5 years ago in reply to Tom Johnson 16214

TI__Mastermind 46460 points

Lawrence,

The reference clock standard HCSL is an industry term first used by Intel. It is the same as the reference clock defined in the PCIE CEM 2.0 standard in section 2.1. Since the single-ended swing of the HCSL clock signals range from 0V to 0.7V, we recommend DC-coupling. Other clock sources can be used but they may need to be AC-coupled and possibly scaled to meet the single-ended voltage limits. Also note that AC-coupled solutions may need a DC bias added at the receiver pins to hold the proper DC levels at the pins. This is discussed in the 2nd E2E post above.

Tom

0 Lawrence Wong over 5 years ago in reply to Tom Johnson 16214

TI__Genius 15000 points

Tom,

Is there any clocking specification for GEN2 that can be shared to the customer or any reference/specification that you can point to? So the general recommendation is External REFCLK Mode, and not Output REFCLK Mode?

Regards,

Lawrence

0 Tom Johnson 16214 over 5 years ago in reply to Lawrence Wong

TI__Mastermind 46460 points

Lawrence,

We do not have a clock source spec in our AM57xx DMs. The only clock source spec is the statement that the clock source must be HCSL or LVDS compliant. We then have the additional statement in section 5.7.12:

5.7.12 PCIEPHY DC Electrical Characteristics
The PCIe interfaces are compliant with the electrical parameters specified in PCI Express
Base Specification Revision 3.0.

Table 2-1 in subsection 2.1.3 of the PCI Express CEM contains the specs that you are requesting.

Tom

0 Tom Johnson 16214 over 5 years ago in reply to Tom Johnson 16214

TI__Mastermind 46460 points

Lawrence,

Use of Internal clock or external clock is a system design consideration. Both options are equally valid.

Tom

Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

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AM5728: PCIe clock requirements