Part Number: TDA2EVM5777
Hi,
I follow the VisionSDK_UserGuide_MemoryMap.pdf try to Modify 512MB Bios Memory map to 1GB Bios Memory map. My evm board is VAYU EVM XC5777X , my vision SDK version is PROCESSOR_SDK_VISION_03_07_00_00_setuplinux.
I rebuild the Appimage and MLO and update to sd card.But it cannot boot up.Here's the boot log.
TDA2xx SBL Boot DPLL Configuration Completed Clock Domain Configuration Completed Module Enable Configuration Completed TI EVM PAD Config Completed DDR Config Completed App Image Download Begins SD Boot - file open completed successfully MPU CPU0 Image Load Completed IPU1 CPU0 Image Load Completed IPU1 CPU1 Image Load Completed IPU2 CPU0 and CPU1 Image Load Completed DSP1 Image Load Completed DSP2 Image Load Completed EVE1 Image Load Completed EVE2 Image Load Completed EVE3 Image Load Completed EVE4 Image Load Completed App Image Download Completed Putting MPU CPU1 in Off mode EVE MMU configuration completed EVE MMU configuration completed EVE MMU configuration completed EVE MMU configuration completed ***************************************************************** PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles SBL Initial Config Cycles - 144545 (12.33 ms) SOC Init Cycles - 170703 (14.56 ms) DDR Config Clock Cycles - 43425 (3.70 ms) App Image Load Cycles - 50179923 (4282.2 ms) Slave Core Bootup Cycles - 208031 (17.75 ms) SBL Boot-up Cycles - 50747687 (4330.46 ms) Time at which SBL started IPU1_0 - 150587 (4595.55 ms) ***************************************************************** Jumping to MPU CPU0 App
It just stop here.............
Here is my git diff
diff --git a/apps/build/tda2xx/mem_segment_definition_bios.xs b/apps/build/tda2xx/mem_segment_definition_bios.xs
index 9dda063..bf3b5ae 100755
--- a/apps/build/tda2xx/mem_segment_definition_bios.xs
+++ b/apps/build/tda2xx/mem_segment_definition_bios.xs
@@ -18,7 +18,7 @@ function getMemSegmentDefinition_external(core)
MB=KB*KB;
DDR3_ADDR = 0x80000000;
- DDR3_SIZE = 512*MB;
+ DDR3_SIZE = 1024*MB;
/*
* In case of ECC_FFI_INCLUDE, DDR3_BASE_ADDR_1 and DDR3_BASE_SIZE_1
@@ -27,7 +27,7 @@ function getMemSegmentDefinition_external(core)
* If this DDR3_BASE_SIZE_0 is changed, update Ipu1_0.cfg
*/
DDR3_BASE_ADDR_0 = DDR3_ADDR;
- DDR3_BASE_SIZE_0 = 507*MB;
+ DDR3_BASE_SIZE_0 = 512*MB;
/* The start address of the second mem section should be 16MB aligned.
* This alignment is a must as a single 16MB mapping is used for EVE
@@ -42,7 +42,7 @@ function getMemSegmentDefinition_external(core)
* in non-cached virtual address of
* DDR3_BASE_ADDR_1 + 512*MB
*/
- DDR3_BASE_ADDR_1 = DDR3_BASE_ADDR_1+512*MB;
+ /*DDR3_BASE_ADDR_1 = DDR3_BASE_ADDR_1+512*MB;*/
}
DSP1_L2_SRAM_ADDR = 0x40800000;
@@ -189,35 +189,18 @@ function getMemSegmentDefinition_external(core)
* be kept constant across all platforms and should match the increment
* to heapStats.heapSize in utils_xmc_mpu.c
*/
- EVE1_VECS_ADDR = DDR3_BASE_ADDR_0;
- EVE1_CODE_ADDR = EVE1_VECS_ADDR + EVE1_VECS_SIZE;
- EVE1_DATA_ADDR = EVE1_CODE_ADDR + EVE1_CODE_SIZE;
- EVE2_VECS_ADDR = EVE1_DATA_ADDR + EVE1_DATA_SIZE;
- EVE2_CODE_ADDR = EVE2_VECS_ADDR + EVE2_VECS_SIZE;
- EVE2_DATA_ADDR = EVE2_CODE_ADDR + EVE2_CODE_SIZE;
- EVE3_VECS_ADDR = EVE2_DATA_ADDR + EVE2_DATA_SIZE;
- EVE3_CODE_ADDR = EVE3_VECS_ADDR + EVE3_VECS_SIZE;
- EVE3_DATA_ADDR = EVE3_CODE_ADDR + EVE3_CODE_SIZE;
- EVE4_VECS_ADDR = EVE3_DATA_ADDR + EVE3_DATA_SIZE;
- EVE4_CODE_ADDR = EVE4_VECS_ADDR + EVE4_VECS_SIZE;
- EVE4_DATA_ADDR = EVE4_CODE_ADDR + EVE4_CODE_SIZE;
- NDK_DATA_ADDR = EVE4_DATA_ADDR + EVE4_DATA_SIZE;
+
+ NDK_DATA_ADDR = DDR3_BASE_ADDR_0 + 16*MB;
IPU1_1_CODE_ADDR = NDK_DATA_ADDR + NDK_DATA_SIZE;
IPU1_0_CODE_ADDR = IPU1_1_CODE_ADDR + IPU1_1_CODE_SIZE;
IPU2_CODE_ADDR = IPU1_0_CODE_ADDR + IPU1_0_CODE_SIZE;
- DSP1_CODE_ADDR = IPU2_CODE_ADDR + IPU2_CODE_SIZE;
- DSP2_CODE_ADDR = DSP1_CODE_ADDR + DSP1_CODE_SIZE;
- IPU1_1_DATA_ADDR = DSP2_CODE_ADDR + DSP2_CODE_SIZE;
+ IPU1_1_DATA_ADDR = IPU2_CODE_ADDR + IPU2_CODE_SIZE;
IPU1_0_DATA_ADDR = IPU1_1_DATA_ADDR + IPU1_1_DATA_SIZE;
IPU2_DATA_ADDR = IPU1_0_DATA_ADDR + IPU1_0_DATA_SIZE;
- DSP1_DATA_ADDR = IPU2_DATA_ADDR + IPU2_DATA_SIZE;
- DSP2_DATA_ADDR = DSP1_DATA_ADDR + DSP1_DATA_SIZE;
- A15_0_DATA_ADDR = DSP2_DATA_ADDR + DSP2_DATA_SIZE;
+ A15_0_DATA_ADDR = IPU2_DATA_ADDR + IPU2_DATA_SIZE;
SR1_BUFF_ECC_ASIL_ADDR = A15_0_DATA_ADDR + A15_0_DATA_SIZE;
SR1_BUFF_ECC_QM_ADDR = SR1_BUFF_ECC_ASIL_ADDR + SR1_BUFF_ECC_ASIL_SIZE;
- DSP1_DATA_ADDR_2 = SR1_BUFF_ECC_QM_ADDR + SR1_BUFF_ECC_QM_SIZE;
- DSP2_DATA_ADDR_2 = DSP1_DATA_ADDR_2 + DSP1_DATA_SIZE_2;
- SR1_BUFF_NON_ECC_ASIL_ADDR = DSP2_DATA_ADDR_2 + DSP2_DATA_SIZE_2;
+ SR1_BUFF_NON_ECC_ASIL_ADDR = SR1_BUFF_ECC_QM_ADDR + SR1_BUFF_ECC_QM_SIZE;
SR1_FRAME_BUFFER_ADDR = SR1_BUFF_NON_ECC_ASIL_ADDR + SR1_BUFF_NON_ECC_ASIL_SIZE;
/* Non Cached Section */
@@ -234,6 +217,26 @@ function getMemSegmentDefinition_external(core)
HDVPSS_DESC_ADDR = SYSTEM_AUTOSAR_IPC_SHM_ADDR + SYSTEM_AUTOSAR_IPC_SHM_SIZE;
OPENVX_SHM_ADDR = HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE;
+ EVE1_VECS_ADDR = DDR3_BASE_ADDR_1 + 16*MB;
+ EVE1_CODE_ADDR = EVE1_VECS_ADDR + EVE1_VECS_SIZE;
+ EVE1_DATA_ADDR = EVE1_CODE_ADDR + EVE1_CODE_SIZE;
+ EVE2_VECS_ADDR = EVE1_DATA_ADDR + EVE1_DATA_SIZE;
+ EVE2_CODE_ADDR = EVE2_VECS_ADDR + EVE2_VECS_SIZE;
+ EVE2_DATA_ADDR = EVE2_CODE_ADDR + EVE2_CODE_SIZE;
+ EVE3_VECS_ADDR = EVE2_DATA_ADDR + EVE2_DATA_SIZE;
+ EVE3_CODE_ADDR = EVE3_VECS_ADDR + EVE3_VECS_SIZE;
+ EVE3_DATA_ADDR = EVE3_CODE_ADDR + EVE3_CODE_SIZE;
+ EVE4_VECS_ADDR = EVE3_DATA_ADDR + EVE3_DATA_SIZE;
+ EVE4_CODE_ADDR = EVE4_VECS_ADDR + EVE4_VECS_SIZE;
+ EVE4_DATA_ADDR = EVE4_CODE_ADDR + EVE4_CODE_SIZE;
+ DSP1_CODE_ADDR = EVE4_DATA_ADDR + EVE4_DATA_SIZE;
+ DSP2_CODE_ADDR = DSP1_CODE_ADDR + DSP1_CODE_SIZE;
+ DSP1_DATA_ADDR = DSP2_CODE_ADDR + DSP2_CODE_SIZE;
+ DSP2_DATA_ADDR = DSP1_DATA_ADDR + DSP1_DATA_SIZE;
+ DSP1_DATA_ADDR_2 = DSP2_DATA_ADDR + DSP2_DATA_SIZE;
+ DSP2_DATA_ADDR_2 = DSP1_DATA_ADDR_2 + DSP1_DATA_SIZE_2;
+
+
if ((SR1_FRAME_BUFFER_ADDR + SR1_FRAME_BUFFER_SIZE) > (DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0))
{
throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
diff --git a/links_fw/src/rtos/bios_app_common/tda2xx/a15_0/a15_0.cfg b/links_fw/src/rtos/bios_app_common/tda2xx/a15_0/a15_0.cfg
index f54833e..988a9e0 100755
--- a/links_fw/src/rtos/bios_app_common/tda2xx/a15_0/a15_0.cfg
+++ b/links_fw/src/rtos/bios_app_common/tda2xx/a15_0/a15_0.cfg
@@ -162,7 +162,7 @@ attrs2.attrIndx = 0; // Non-cache, normal memory
// Set the descriptor for each entry in the address range
for (var i=0xA0000000; i < 0xC0000000; i = i + 0x00200000) {
// Each 'BLOCK' descriptor entry spans a 2MB address range
- Mmu.setSecondLevelDescMeta(i, i-0x20000000, attrs2);
+ Mmu.setSecondLevelDescMeta(i, i, attrs2);
}
// Region for NDK packet data buffers.
diff --git a/links_fw/src/rtos/bios_app_common/tda2xx/ipu1_0/Ammu1_bios.cfg b/links_fw/src/rtos/bios_app_common/tda2xx/ipu1_0/Ammu1_bios.cfg
index 7809abc..685a934 100644
--- a/links_fw/src/rtos/bios_app_common/tda2xx/ipu1_0/Ammu1_bios.cfg
+++ b/links_fw/src/rtos/bios_app_common/tda2xx/ipu1_0/Ammu1_bios.cfg
@@ -204,13 +204,13 @@ function init()
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0xA0000000;
- entry.translatedAddress = 0x80000000;
+ entry.translatedAddress = 0xA0000000;
entry.size = AMMU.Large_512M;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;
-/*
+
var entry = AMMU.largePages[3];
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
@@ -221,6 +221,6 @@ function init()
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;
-*/
+
}
diff --git a/links_fw/src/rtos/bios_app_common/tda2xx/ipu2/Ammu2_bios.cfg b/links_fw/src/rtos/bios_app_common/tda2xx/ipu2/Ammu2_bios.cfg
index 21d55cc..f44a488 100644
--- a/links_fw/src/rtos/bios_app_common/tda2xx/ipu2/Ammu2_bios.cfg
+++ b/links_fw/src/rtos/bios_app_common/tda2xx/ipu2/Ammu2_bios.cfg
@@ -204,13 +204,13 @@ function init()
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0xA0000000;
- entry.translatedAddress = 0x80000000;
+ entry.translatedAddress = 0xA0000000;
entry.size = AMMU.Large_512M;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;
-/*
+
var entry = AMMU.largePages[3];
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
@@ -221,5 +221,5 @@ function init()
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;
-*/
+
}
\ No newline at end of file
diff --git a/links_fw/src/rtos/links_ipu/system/system_bsp_init.c b/links_fw/src/rtos/links_ipu/system/system_bsp_init.c
index 55eb2b8..083ba64 100644
--- a/links_fw/src/rtos/links_ipu/system/system_bsp_init.c
+++ b/links_fw/src/rtos/links_ipu/system/system_bsp_init.c
@@ -47,10 +47,10 @@ Limited License.
DISCLAIMER.
- THIS SOFTWARE IS PROVIDED BY TI AND TIS LICENSORS "AS IS" AND ANY EXPRESS OR
+ THIS SOFTWARE IS PROVIDED BY TI AND TI�S LICENSORS "AS IS" AND ANY EXPRESS OR
IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- IN NO EVENT SHALL TI AND TIS LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ IN NO EVENT SHALL TI AND TI�S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
@@ -292,10 +292,10 @@ Int32 System_bspInit(void)
vpsInitPrms.physBaseAddr = 0x80000000U;
vpsInitPrms.isAddrTransReq = FALSE;
#else
- vpsInitPrms.virtBaseAddr = 0xA0000000U;
+ vpsInitPrms.virtBaseAddr = 0x80000000U;
vpsInitPrms.physBaseAddr = 0x80000000U;
/* if Virtual address != Physical address then enable translation */
- vpsInitPrms.isAddrTransReq = TRUE;
+ vpsInitPrms.isAddrTransReq = FALSE;
#endif
Vps_printf(" SYSTEM: VPDMA Descriptor Memory Address translation"
" ENABLED [0x%08x -> 0x%08x]\n",
It 's same as the user guide expect build/rtos/makerules/build_sbl.mk.My sources has no this file.
So,is my step right? why the board cannot boot up?
Regards
