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Original question:

TMS320C6678: VCNTL[3:0] VID Interface timing

TMS320C6652: VCTRL default voltage at Power on

Divy
Intellectual 380 points
Part Number: TMS320C6652
Other Parts Discussed in Thread: LM10011, TPS544C25,

Hi ,

I am planning to use TPS544C25 and LM10011 to power up TMS320C6652.

I understand from Datasheet the CVDD nominal voltage at start up is 1.1V. Please clarify the following

1. VCTRL[0:3] shall be default high[1111] before the smart reflex sequence starts.

2. VCTRL [0:3] timing sequence will be managed by the processor at power on.

Regards,

Divy

  • 0
    TI__Mastermind 42545 points

    Hi Divy,

    1) The pull up resistors required on the VCTRL pins will keep these signals high until the smart reflex sequence starts. 

    2) Once the power sequencing completes and the C6652 has released from reset, the processor will execute the sequence on the VCTRL lines to modify the voltage to the necessary value.

    Regards, Bill