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AM4378: DSS configuration

kw
Prodigy 115 points
Part Number: AM4378

I’m currently working on configuring the DSS for the AM4378 and had a few questions:

  1.  What is the recommended way to enable the clocks needed to bring the DSS out of reset? Sections 13.4.1 and 13.5.2.2.2 of the TRM state that the following registers need to be set to enable all the display clocks required to bring the DSS out of reset:
  • PRCM.CM_FCLKEN_DSS[0] EN_DSS1 = 0x1
  • PRCM.CM_FCLKEN_DSS[1] EN_DSS2 = 0x1
  • PRCM.CM_FCLKEN_DSS[2] EN_TV = 0x1
  • PRCM.CM_ICLKEN_DSS[0] EN_DSS = 0x1
  • PRCM.CM_CLKEN_PLL[18:16] EN_PERIPH_DPLL = 0x7

 However, I can’t seem to find any other references to those registers and bitfields in the TRM. 

  1. Which of the bits of the DSS.DISPC_CTRL register are shadowed?  The footnote in Table 13-21 indicates that only a subset of the bits are shadowed, but I couldn’t find which specific bits it was referring to. 

  1. What is the preferred way to configure the DSS for Bypass Mode (RFBI disabled)?  Is configuring the GPOUT bits as shown in Table 13-6 sufficient, or do I need to ensure that the RFBI_CTRL.EN and RFBI_CTRL.BYPASS_MODE bits are appropriately set as well?
  1. In Table 13-63, the description for GFX_BURST_SIZE notes that a value of 3 equals ‘3’.  Is the value of 3 reserved or is it an additional burst size?
  1. What is the LCD Enable signal referred to by LCD_EN_POL and LCD_EN_SIGNAL in Table 13-47?  The DSS pin list table (Table 13-4) doesn’t indicate the existence of an LCD enable pin, with the closest thing being the AC Bias Enable pin.
  1. What is the valid range for the PCD bitfield in the DSS.DISPC_DIVISOR register?  In Table 13-56, the description for the bitfield first indicates a valid range of 1 to 255, but then goes on to say that values of 0 and 1 are invalid. 
  • 0
    TI__Guru* 80240 points

    1. Those clock gates are not present in the AM43xx. This text was inadvertently left in from a previous device. None of the clocks to the DSS are gated. See figure 13-1 DSS Integration. 

    2. The note only refers to the DISPC_CTRL register, as this register has a couple of bits associated with controlling the
    shadow register loading. See the register description for more details.

    3. It is best to configure all those bits mentioned. The GPOUT bits control the data path at the subsystem level,
    while the other bits are module level control. Section 13.4.4.2 has more details on the module control.

    4. That's a typo. Value of 3 for GFX_BURST_SIZE is reserved.  Will be fixed in next TRM release

    5. LCD_EN_POL and LCD_EN_SIGNAL are not used in this design. Those bits should be written with 0.

    6. The DSS controller can support values from 1 to 255, but the limitation on the AM43xx device is 100MHz external pixel clock.  Since the pixel clock is source from the DSSDISPCDPLLCLK, which is either 200MHz or 192MHz (see Fig 13-1 and table 13-2), PCD should be a minimum of 2 to ensure the external pixel clock is 100MHz or lower. I will change the wording in the bit field to make it clearer.

    Regards,

    James