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[TDA4VM] About SPI timing

Manwoo Kim
Intellectual 565 points

Hi,

I have questions about SPI timing.

Our board has SPI interface between MCU domain of TDA4 and AP domain of TDA4. (MOSI : F25-->V25, MISO : W24-->F28, CS : F27-->W27, CLK : F26-->W29)

1) This interface's setup time(SPI_D valid before SPI_CLK active edge) is sholud be longer than 2.9ns according to datasheet(Table 5-75. Timing Requirements for SPI).

    As I attached (1.spi-i-48mhz-cs-time, 2.spi-i-48mhz-mode0-fail, 3. spi-i-48mhz-mode2-ok), our interface can't meet the setup time when clk is 48MHz. (spi-i-48mhz-mode0-fail).

    Surely, we can change the mode, and we can meet the setup time by setting mode2 (spi-i-48mhz-mode2-ok), 24MHz is also ok.

 Q) Could we change the timing of MOSI or MISO?(ex. change some registers) Should it work normally at 48MHz?

2) Delay time (SPI_CSi active to SPI_CLK first edge, SPI_CLK last edge to SPI_CSi inactive) looks so long. (please see the spi-i-48mhz-cs-time)

  Q) Is it normal?

Please give me a comment!

Thanks,

Manwoo Kim

  • 0
    TI__Genius 15120 points

    Hi Manwoo Kim,

    1. I don't know for a register for MOSI timing. The main issue here, I think,  is that 48 MHz is the max frequency and this implies the PCB must be carefully designed .

    2. I think this is is normal if SINGLE mode (one master, one slave) was chosen in software.

    Also, didn't you consider use the internal connected MCSPIs? MCSPI4 has a permanent connection to MCU_MCSPI2 and MCSPI3 can optionally be muxed to MCU_MCSPI1 internally. Please refer to Figure 12-313. MCSPI Overview in TRM.

    Regards,

    Stan

  • 0 in reply to Stanislav Stilyanov
    Intellectual 565 points

    Hi, Stan.

    Thanks for your reply.

    Does "Don't know for a register for MOSI timing" mean there is no register for MOSI/MISO timing?

    Thanks,

    Manwoo Kim

  • 0 in reply to Manwoo Kim
    TI__Genius 15120 points

    I've scrolled through MCSPI registers and PADCONF registers. I didn't find a setting to improve timing in MCSPI, but in the PADCONF registers for CLK and MOSI pins, you can try change the Drive Strength setting. I.e. bits 20:19 DRV_STR. I see it is 0x0 by default, so you can increase it gradually to see if any improvement. I don't know however if this will work in this case.

    Regards,

    Stan

  • 0 in reply to Manwoo Kim
    TI__Expert 4015 points

    Manwoo,

    Have you taken the action proposed by Stan to check if drive strength affects setup time?  Also, I noticed that in image 2, the setup time is measured from MISO=90%, but in image 2 it is measured from MISO=50%.  Timings in the data sheet are based on 50% levels.

    -Zack

  • 0 in reply to Stanislav Stilyanov
    Intellectual 565 points

    Hi, Stan.

    Thanks for your reply.

    I will try to do your solution, and then notice you.

    Thanks,

    Manwoo Kim