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TIDEP-01002: 1280x720 HDMI display by VisionSDK DSS not correct

Part Number: TIDEP-01002

hi all experts,

my EVM board is TIDEP-01002, now we have a projector, it support HDMI 1280x720 input.

and we run visionSDK 0304 on M4 core to control the DSS, and linux side graphy image by VDRM.

now we have the problem of projector can not show image correctly.

i create pipeline as following, use VID2 to display. 

DispDistSrc_Infotainment-> Display_vid2

i set the VDRM in dts as following:

vdrm1: vdrm@1 {
   /* For Android presentation mode window on 720p HDMI */
   compatible = "ti,dra7-vdrm";
   vdrm1_crtc0: crtc@0 {
    compatible = "ti,dra7-vdrm-crtc";
    x-res = <1280>;
    y-res = <720>;
    refresh = <50>;
    supported-formats = <
     DT_DRM_FORMAT_RGB565   DT_DRM_FORMAT_RGBX4444 DT_DRM_FORMAT_XRGB4444
     DT_DRM_FORMAT_RGBA4444 DT_DRM_FORMAT_ARGB4444 DT_DRM_FORMAT_XRGB1555
     DT_DRM_FORMAT_ARGB1555 DT_DRM_FORMAT_RGB888   DT_DRM_FORMAT_RGBX8888
     DT_DRM_FORMAT_XRGB8888 DT_DRM_FORMAT_RGBA8888 DT_DRM_FORMAT_ARGB8888
     DT_DRM_FORMAT_NV12     DT_DRM_FORMAT_YUYV     DT_DRM_FORMAT_UYVY
    >;
   };
  };

and i set the VID2 parameters as following:

    pUcObj->Display_vid2Prm.rtParams.tarWidth         = 1280;
    pUcObj->Display_vid2Prm.rtParams.tarHeight        = 720;
    pUcObj->Display_vid2Prm.rtParams.posX             = 0;
    pUcObj->Display_vid2Prm.rtParams.posY             = 0;
    pUcObj->Display_vid2Prm.displayId                 = DISPLAY_LINK_INST_DSS_VID2;

i set the display parameters as following :

/* HDMI Resolution and assigned pipeline */
    pVsObj->mDisplayPrms[1].displayType = CHAINS_DISPLAY_TYPE_HDMI_720P; //CHAINS_DISPLAY_TYPE_HDMI_1080P;
    pVsObj->mDisplayPrms[1].numPipes = 1;
 // Infotainment
    pVsObj->mDisplayPrms[1].pipeID[0] = SYSTEM_DSS_DISPC_PIPE_VID2;
    pVsObj->mDisplayPrms[1].zOrderPipeID[0] = SYSTEM_DSS_DISPC_ZORDER0;
 if (pMultiPrm[i].displayType == CHAINS_DISPLAY_TYPE_HDMI_720P)
  {
   pPrm->deviceId = DISPLAYCTRL_LINK_USE_HDMI;
   pVInfo->vencId = SYSTEM_DCTRL_DSS_VENC_HDMI;
   pVInfo->outputPort = SYSTEM_DCTRL_DSS_HDMI_OUTPUT;
   pVInfo->vencOutputInfo.vsPolarity       =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;
   pVInfo->vencOutputInfo.hsPolarity       =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;
   /* Below are of dont care for EVM LCD */
   pVInfo->vencOutputInfo.fidPolarity      =   SYSTEM_DCTRL_POLARITY_ACT_LOW;
   pVInfo->vencOutputInfo.actVidPolarity   =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;
   pVInfo->vencOutputInfo.dataFormat       =   SYSTEM_DF_RGB24_888;
   pVInfo->vencOutputInfo.dvoFormat        =
    SYSTEM_DCTRL_DVOFMT_GENERIC_DISCSYNC;
   pVInfo->vencOutputInfo.videoIfWidth     =   SYSTEM_VIFW_24BIT;
   pVInfo->vencOutputInfo.pixelClkPolarity =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;
   pVInfo->vencOutputInfo.aFmt             =   SYSTEM_DCTRL_A_OUTPUT_MAX;
   pVInfo->mInfo.standard                  =   SYSTEM_STD_720P_60;
   /* Configure overlay params */
   ovlyPrms[i].vencId                        = pVInfo->vencId;
  }
and i run the ti kmscube demo,  the uncorrect show as following:
i dump the data from DispDistSrc_Infotainment link, it correct and it is 1280x720 resolution. so the problem is in display link.
(1) DSS control by M4, HDMI is 1920x1080, it can show correctly if i change the above setting for 1080p.
(2) Linux control the DSS, HDMI can show correctly (both 1920x1080p and 1280 x 720p).
(3) DSS control by M4, HDMI is 1280x720, and i setting the parameters as the above, it can not show correctly.
so could anyone give me some hints?
best regards!

  • Did you program the display link parameters timing values for 1280x720? For example the hws, hfp, hbp etc?

  • hi

    i use the visionsdk default setting,

    i check the code in  pdk_01_10_00_08/packages/ti/drv/vps/src/vpslib/hal/src/vpshal_dssHdmi.c, the parameters setting as following:

    {{1280, 720,  0, 74250,  110, 220, 40, 5,  20, 5,
          VPSHAL_HDMI_HDMI}, 4},

    if not run visionsdk, linux kernel can drive HDMI correctly,  so  where can i get the right parameters? so i can use these paras setting 

    in vision sdk.

    best regards!

  • hi expert

    i connect the projector with my computer, and i use softMCCS tool to get the EDID data, as following:

    they are match with the vision sdk HDMI setting, and i also check my display link creating parameter, as following, they are correct.

     [HOST] [IPU2  ]      3.821631 s:  DISPLAY 1: Create in progress, res = 1280 x 720 !!!
     [HOST] [IPU2  ]      3.821783 s: DisplayLink_drvDisplayCreate VPS_DISP_INST_DSS_VID2
     [HOST] [IPU2  ]      3.822058 s: DisplayLink_drvDisplayCreate Chinfo: 1280x720, rtParams: 1280x720, pitch0: 5120

    when the full screen is green color, the uncorrect show as following:

    so i am so confused, what the problem?

    best regards!

  • hi Subhajit Paul,

    i dump the DSS registers value as following:

    [root@x home]# ./debug_dss_clockdumps.sh

    =====================DSS clock script===================
    Dumps internal clocks and muxes of DSS
    CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002AA
    video1 PLL :  Enabled
    video2 PLL :  Disabled
    HDMI   PLL :  Enabled
    DSI1_A_CLK mux : DPLL HDMI
    DSI1_B_CLK mux : DPLL video2
    DSI1_C_CLK mux : DPLL Video1
    DSS_CTRL (0x58000040) = 0x00090000
     2: LCD1 clk switch :  DSS clk
     3: LCD2 clk switch :  DSS clk
    10: LCD3 clk switch :  DSI1_C_CLK
     1: func clk switch :  DSS clk
    13: DPI1 output     :  LCD1
    DSS_STATUS (0x5800005C) = 0x02408A81
    DSI_CLK_CTRL (0x58004054) = 0x80004001
    CM_DSS_CLKSTCTRL (0x4A009100) = 0x00061F03
    CM_DSS_DSS_CLKCTRL (0x4A009120) = 0x00003F02
    ========================================================
    Register dump for DPLL video1
    Warning: chip not recognized, running in safe mode (only platform-generic functions allowed).
    |----------------------------|
    | Address (hex) | Data (hex) |
    |----------------------------|
    | 0x58004300    | 0x00000018 |
    | 0x58004304    | 0x00002683 |
    | 0x58004308    | 0x00000000 |
    | 0x5800430C    | 0x00EF78FE |
    | 0x58004310    | 0x00E16108 |
    | 0x58004314    | 0x00000007 |
    | 0x58004318    | 0x00000000 |
    | 0x5800431C    | 0x00000000 |
    | 0x58004320    | 0x00000000 |
    |----------------------------|
    Details for DPLL video1
    PLL status  :  Locked
    M4 hsdiv(1) :  Active
    M5 hsdiv(2) :  inactive
    M6 hsdiv(3) :  Active
    M7 hsdiv(4) :  inactive
    PLL_REGM   =  1980
    PLL_REGN   =  127
    M4 DIV     =  7
    M6 DIV     =  7
    M7 DIV     =  0
    Clock calculations (DPLL video1)
    sysclk = 20000000
    DCO clk = sysclk * 2 * REGM / (REGN + 1) = 618750000
    M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 77343750
    M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 77343750
    M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 0
    ========================================================
    Register dump for DPLL hdmi
    Warning: chip not recognized, running in safe mode (only platform-generic functions allowed).
    |----------------------------|
    | Address (hex) | Data (hex) |
    |----------------------------|
    | 0x58040200    | 0x00000018 |
    | 0x58040204    | 0x00000003 |
    | 0x58040208    | 0x00000000 |
    | 0x5804020C    | 0x0004A41E |
    | 0x58040210    | 0x00602004 |
    | 0x58040214    | 0x00000000 |
    | 0x58040218    | 0x00000000 |
    | 0x5804021C    | 0x00000000 |
    | 0x58040220    | 0x00040000 |
    |----------------------------|
    Details for DPLL hdmi
    PLL status  :  Locked
    M4 hsdiv(1) :  inactive
    M5 hsdiv(2) :  inactive
    M6 hsdiv(3) :  inactive
    M7 hsdiv(4) :  inactive
    PLL_REGM   =  594
    PLL_REGN   =  15
    M4 DIV     =  0
    M6 DIV     =  0
    M7 DIV     =  0
    PLL_REGM2  =  1
    PLL_REGM_F =  1
    PLL_SD  =  0
    HDMI_SSC_CONFIGURATION1(should be zero) 0x00000000
    HDMI_SSC_CONFIGURATION2(should be zero) 0x00000000
    Clock calculations (DPLL hdmi)
    sysclk = 20000000
    CLKOUT = sysclk * REGM / (REGM2 * (REGN + 1)) = 742500000
    ========================================================
    Clock O/P of MUXes
    ./debug_dss_clockdumps.sh: line 309: arithmetic syntax error
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    This board connect two display, one 1920x720 LCD and 1280x720 HDMI.
    i also dump the DSS registers value  when not run visionSDK and 1280x720 HDMI can show normally as following:
    DSI1_C_CLK mux : DPLL Video1
    DSS_CTRL (0x58000040) = 0x00080000
     2: LCD1 clk switch :  DSS clk
     3: LCD2 clk switch :  DSS clk
    10: LCD3 clk switch :  DSI1_C_CLK
     1: func clk switch :  DSS clk
    13: DPI1 output     :  HDMI
    DSS_STATUS (0x5800005C) = 0x02408A81
    DSI_CLK_CTRL (0x58004054) = 0x80004001
    CM_DSS_CLKSTCTRL (0x4A009100) = 0x00040F03
    CM_DSS_DSS_CLKCTRL (0x4A009120) = 0x00001702
    ========================================================
    Register dump for DPLL video1
    Warning: chip not recognized, running in safe mode (only platform-generic functions allowed).
    |----------------------------|
    | Address (hex) | Data (hex) |
    |----------------------------|
    | 0x58004300    | 0x00000018 |
    | 0x58004304    | 0x00002603 |
    | 0x58004308    | 0x00000000 |
    | 0x5800430C    | 0x000A4046 |
    | 0x58004310    | 0x00E06008 |
    | 0x58004314    | 0x0000000E |
    | 0x58004318    | 0x00000000 |
    | 0x5800431C    | 0x00000000 |
    | 0x58004320    | 0x00000000 |
    |----------------------------|
    Details for DPLL video1
    PLL status  :  Locked
    M4 hsdiv(1) :  inactive
    M5 hsdiv(2) :  inactive
    M6 hsdiv(3) :  Active
    M7 hsdiv(4) :  inactive
    PLL_REGM   =  1312
    PLL_REGN   =  35
    M4 DIV     =  0
    M6 DIV     =  14
    M7 DIV     =  0
    Clock calculations (DPLL video1)
    sysclk = 20000000
    DCO clk = sysclk * 2 * REGM / (REGN + 1) = 1457777777
    M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 0
    M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 97185185
    M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 0
    ========================================================
    Register dump for DPLL hdmi
    Warning: chip not recognized, running in safe mode (only platform-generic functions allowed).
    |----------------------------|
    | Address (hex) | Data (hex) |
    |----------------------------|
    | 0x58040200    | 0x00000018 |
    | 0x58040204    | 0x00000003 |
    | 0x58040208    | 0x00000000 |
    | 0x5804020C    | 0x0004D40E |
    | 0x58040210    | 0x00602004 |
    | 0x58040214    | 0x00001800 |
    | 0x58040218    | 0x00000000 |
    | 0x5804021C    | 0x00000000 |
    | 0x58040220    | 0x000B0000 |
    |----------------------------|
    Details for DPLL hdmi
    PLL status  :  Locked
    M4 hsdiv(1) :  inactive
    M5 hsdiv(2) :  inactive
    M6 hsdiv(3) :  inactive
    M7 hsdiv(4) :  inactive
    PLL_REGM   =  618
    PLL_REGN   =  7
    M4 DIV     =  0
    M6 DIV     =  0
    M7 DIV     =  0
    PLL_REGM2  =  2
    PLL_REGM_F =  2
    PLL_SD  =  6
    HDMI_SSC_CONFIGURATION1(should be zero) 0x00000000
    HDMI_SSC_CONFIGURATION2(should be zero) 0x00000000
    Clock calculations (DPLL hdmi)
    sysclk = 20000000
    CLKOUT = sysclk * REGM / (REGM2 * (REGN + 1)) = 772500000
    ========================================================
    Clock O/P of MUXes
    ./debug_dss_clockdumps.sh: line 309: arithmetic syntax error
    the red line is diff of two DSS regiters's log. 
    can you help me figure out the problem?
    best regards!