TDA3LX: IBIS simulation

Hi,

What interface or interfaces are you trying to simulate?

There is not a step-by-step procedure to use the IBIS model, as this would likely vary depending on the simulation software used. However, it is possible that the simulation software provides guidance (either through documentation or as a step-by-step feature) in running simulations. 

Best regards,
Kevin

Hi.

Sorry I do not quite understand the meaning of "interface" in this context...

I am running a Time Analysis Simulation on CST Studio to study the resulting Eye Diagrams from different PCB routings (a deliberately bad design, and an optimized one) on a PCB design that has the TDA3LX BGA on it.

I've repeated the simulations for a number of traces, but some of them return a worse result for the optimized routing (as checked through the Eye Properties log file).
This is rather odd because I expected a significant difference between the Eye Diagram results for a bad and good routing.  The others returned negligible differences. Some also returned a negative Eye Crossing Percentage. 

Hence, I am requesting for assistance to see what other simulations settings should be applied to the simulations, such as including any other IBIS files within the simulation.

I have only been using the tda3lx_abs.ibs IBIS model for the TDA3LX BGA, and I am looking to see if my simulations have been carried out properly.

TLDR: Are other IBIS models needed to run an analysis on a DDR1 trace that connects a component to the TDA3LX BGA?
What are some settings that I should pay attention to during simulations?

(Simulation settings: PRBS of 8 bits, Signal Period of 1.876ns)

Best regards. 

>>Sorry I do not quite understand the meaning of "interface" in this context...

There are several IO on the TDA3 part, so the question was trying to understand what is being simulated (ex: DDR, MMC, etc.).

>>I am requesting for assistance to see what other simulations settings should be applied to the simulations, such as including any other IBIS files within the simulation. Are other IBIS models needed to run an analysis on a DDR1 trace that connects a component to the TDA3LX BGA?
What are some settings that I should pay attention to during simulations?

If you are simulating DDR, you should also be using an IBIS model for the DDR memory that corresponds to the part on the PCB. Are you simulating writes, reads, both? What models are you using? The models correspond to different IO settings such as drive strength, ODT, and slew rate. 

Best regards,
Kevin

I've checked with the documentation, and this particular trace DDR1_A0 seems to be an output type of signal, so it should be Write type?

As for the "models", I am not sure where to see the information for the DDR1_A0's models.

>>If you are simulating DDR, you should also be using an IBIS model for the DDR memory that corresponds to the part on the PCB.

I see. It seems that I am indeed lacking such a IBIS model (I only have the tda3x_abs.ibs model). Where could I obtain the necessary IBIS model? I am uncertain as well as to which IBIS models would be appropriate.

Regards.

Hi Kyle.

I've proceeded to obtain other IBIS models for other components, and I believe I have found one of the necessary IBIS model.

My concern is now whether I am placing the correct "buffer model", as detailed below:

If I am running a simulation on a DDR3 trace that is of I/O type, should one of the components be given a READ buffer model, while the other can retain the I/O buffer model?

Context: This trace connects the TDA3LX BGA to MT41K512M16HA-125_IT FBGA. I run a simulation on the trace that connects these 2 components. 
Some of the "buffer models" are DQ_IN_ODT40_1066, DQ_34_1600 etc...

More information is within the attached file.

Hope to have some clarification. 

Thank you.Questions.pptx