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TDA4VM: [TDA4VM] What is the PCIe signaling levels for TDA4VM?

Evan Chuang
Prodigy 170 points
Part Number: TDA4VM

Hi,

I can't find the information from datasheet or TRM

What is the PCIe signaling levels for TDA4VM?

Ex:low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-mode logic (CML)

Evan

  • 0
    TI__Genius 15120 points

    Hi Evan,

    I wasn't able to find the hs buffer type in any document. My guess (Only!) it is CML as I have seen on previous TI SoCs and other devices.

    As seen from the EVM schematic, for PCIe, you only need the AC-coupling serial resistors near the Tx pins.

    Regards,

    Stan

  • 0 in reply to Stanislav Stilyanov
    Prodigy 170 points

    Hi Stan,

    Do you mean the AC-coupling serial CAP near the TX pins. Could you help to confirm internal what is the support CML or LVDS or others...?

    Regarding the PCIE_REFCLK, is it support HCSL or LVDS? Do we need to add AC-coupling serial cap from external clock source?

    Regards,

    Evan

  • 0 in reply to Evan Chuang
    TI__Genius 15120 points

    Evan,

    Do you mean the AC-coupling serial CAP near the TX pins. [yes]

    Could you help to confirm internal what is the support CML or LVDS or others...? [I don't think this is possible. According to TI user documents, and also internal TI documents, it is enough to know that data lane interface IS compatible to PCIe specs and only the AC-coupling is needed.]

    Regarding the PCIE_REFCLK, is it support HCSL or LVDS? [PCIe uses HCSL for 100-MHz clock drivers]

    Do we need to add AC-coupling serial cap from external clock source?  [If using clock generator similar to that in EVM CDCI6214RGET - No]

    Regards,

    Stan