Hi Experts,
Le me clarify a couple of questions for ECC for DDR.
1) According to the TRM www.ti.com/lit/SPRUHZ7, it says "The ECC feature is not available on this device," in 15.3.4.14.
However, the errata http://www.ti.com/lit/SPRZ436 describes the limitation of the ECC function ( Workaround ).
Does this mean the ECC function in AM571x is workable if the workaround is followed?
2) If ECC function is not guaranteed, are there any ways to detect error and correct it without changing CPU?
3) For the errata i922.
When the memory initialization just after ECC enabled, zero must be written with 32bit DDR width.
Is it possible if 16 bit access from IPU, USB, or eMMC through DMA transfer is done.
Or does every write access have to be aligned with 32 bit width for all area where ECC enabled?
Thank you in advance for your kind clarification.
Best regards,
Hitoshi