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GPMC usage - nonmultiplexed, synchronous, burst read/write mode

user3788809
Intellectual 900 points
Part Number: 66AK2G12

Hi,

In terms of GPMC, is it posible to set as nonmultiplexed, synchronous, burst mode?

According to the figure 5-37 (GPMC and NOR Flash—Synchronous Burst Read—4x16-bit) and figure 5-38 (GPMC and NOR Flash—Synchronous Burst Write) of data manual,

GPMC_A (vaild address) is described as "GPMC_A[10:1]" (not GPMC_A[26:1]).

( ↑ Is it mistaken? or is it impossible set as nonmultiplexed?)

Moreover, according to the TRM, there is no description of figure for nonmultiplexed, synchronous, burst read/write case. (All burst mode figures are  described as "multiplexed".)

We are planing to connect with FPGA as nonmultiplexed and synchronous NOR device (burst access).

If it is possoble, which figure should we follow to set the resister and design the timing?

Thanks.

  • 0
    Intellectual 900 points

    I would like to know whether it is possible to use as nonmultiplexed, synchronous, burst mode or not at least.

    Thank you for your corporation.

  • 0
    TI__Mastermind 29810 points

    Hi,

    Non-multiplexed, synchronous, burst mode will burst upto 16-words (16-bit data) when the DMA is used to write data to GPMC. Without DMA, the burst will stop after 4 bytes.

    TRM Figure 7-159. GPMC to 16-Bit Non-Multiplexed Memory shows GPMC_A[27:1] connected to 16-bit A/D non-multiplexed memory A[26:0].

    TRM Figure 7-158. GPMC to 16-Bit Address/Data-Multiplexed Memory shows GPMC_A[27] and GPMC_A[10:1] connected to A/D multiplexed memory A[26:16] (MSBs). GPMC_AD[15:0] transmits the LSBs of the address to memory A/D[15:0].

    TRM Table 7-463. GPMC Pin Multiplexing Options shows the Address bus pins that are used for Multiplexed Address Data 16-Bit Device vs non-multiplexed Address Data 16-Bit Device (complete 28-bit address range)

    For non-multiplexed, GPMC_A[27:1] carries A[27:1]. A0 is not used with 16-bit data on AD[15:0].



    The datasheet figures do appear to have incorrect Address bus ranges.

    Datasheet Figure 5-36, Figure 5-37, Figure 5-38, Figure 5-41, Figure 5-42, Figure 5-43 should replace GPMC_A[10:1] with GPMC_A[27:1]

    Datasheet Figure 5-39 and Figure 5-40. should replace GPMC_A[27:17] with GPMC_A[27], GPMC_A[10:1]

    Datasheet Table 4-4. GPMC Signal Descriptions appears to be correct, and matches TRM Table 7-463. GPMC Pin Multiplexing Options.

    If using WAIT signal, be aware that with GpmcFCLKDivider = 0, WAIT must be valid 1 or 2 cycles before WRITEACCESSTIME, and WAITMONITORINGTIME must be configured as such. See https://e2e.ti.com/support/processors/f/791/p/962631/3557535#3557535

    Regards,
    Mark