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Hi
What is the value of internal pull-up / pull-down resister of GPIOs during HHV?
Thanks.
Is there any insufficient information to response?
(Am I wrong something? I cannot find this value from TRM and data manual)
Regards.
Hi
Let me find the owner to help address this.
Table 5-9, 5-10 in DM is what i think is the typical guidance and schematic checklist has the following
Most signal pins on the 66AK2Gx have internal pulling resistors present by default when the device is in reset. If an external pulling resistor is used to pull the signal high or low in opposition to the internal pulling resistor, it must be of sufficient strength to avoid a mid-voltage condition. A mid-voltage condition results in high-leakage current, which could damage the IO cell.
What are you trying to do with this information? What external PU/PD values are you planning to use?
Regards
Mukul
The forum post linked here (AM572x I/O pullup/pulldown resistor value - Processors forum - Processors - TI E2E support forums
Thank you for your answer.
I am planing to use 4.7kΩ pull-up resister to recognize high level during HHV.
(I guess it is inadequacy.)
Regards.
That is correct when looking at the 66AK in isolation. However, I'd like to highlight the paragraph from the linked thread:
When deciding what value of external resistor to use you must consider the worst case combination of all internal leakage paths of all devices connected to a signal and make sure the external resistor is able to force these internal leakage paths to a potential greater than Vih min, or less than Vil. You must insure the input is not held at a mid-supply potential for long periods of time.
--Paul
On the other hand, as for the schematic of K2G ICE EVM,
why is DP83822IRHBT connected to E10 pin of 66AK possible to recognize that PHY address is "00010"?
Bacause E10 pin has internal pull-down resister whose value is ranging from 15kΩ to 66kΩ (VDSS = 3.3V) during HHV,
I cannot understand the reason why DP83822IRHBT is able to recognize that input level of DP83822IRHBT's 30 pin is high level.
How about this?
Regards.
The schematic snapshot included above shows the RXD0 signal connected to pin 30 of DP83822, pin E10 of 66AK2G12, and external 1k ohm pull-up resistor R397. To determine the resulting logic level we need consider both DP83822 and 66AK2G12 devices have internal pull-downs, where the DP83822 pull-down is typically 9k ohm and the 66AK2G12 pull-down is typically 27.5k ohm. The combined typical pull-down is about 6.8k ohm. The resulting voltage from a 1k ohm pull-up and 6.8k ohm pull-down will be about 2.9V. The VIH min for DP83822 is 1.7V, so the DP83822 RX_D0 input should detect a high logic level for the AD[1] bit.
The other RXD[3:1] signals will be low because all internal and external pulls and pull-downs. Which means the DP83822 RX_D0 should detect a low logic level for the AD[4:2] bits.
From the DP83822 datasheet: PHY address pins PHY_AD[4:1] are multiplexed with RX_D[3:0], and are pulled-down.
Regards,
Paul