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PROCESSOR-SDK-DRA7X: MIRROR Imaging with existing usecase

Part Number: PROCESSOR-SDK-DRA7X

Hello Ti Team, 

We have below usecase and we have two cameras which use Capture links as shown below. With existing usecase can we perform MIRROR Imaging, Please also see the attached Image. 

If yes, Can you please share the detailed information on how to perform this

UseCase: weston_dualcamera_dsswb


Capture -> Display_Video
Capture_1 -> Display_Video1
DispDistSrc_gfx -> Display_gfx
DispDistSrc_vid3 -> Display_vid3
Capture_dsswb -> Alg_SwCrc

BR,

RK

  • Hi Raghu,

    Capture and display does not support Mirror functionality

    One question, do you use Tiler in your memory map? This is because tiler memory space could be used to add this feature.

    Regards,

    Brijesh

  • Hi Brijesh,

    Strictly we dont want to change the usecase. But if this Tiler memory can help to perform Mirroring without changing usecase then we can explore in that direction. 

    How can I check if Tiler memory map is available, can you give pointers ? 

    BR,

    RK

  • Hi Raghu,

    Please check your memory map and see if any section allocated for tiler.

    Regards,

    Brijesh

  • Hi Brijesh, 

    I have checked the Register DISPC_VIDp_BA_j for VID1 and the BA address is changing, confirming Tiler address is there. 

    Can you please confirm on how can we obtain mirroring ?

    11.2.4.7:DISPC Rotation and Mirroring

    This section talks about mirroring Our Goal is to achieve 0 degree rotation + Mirroring on VID 1 pipeline.

    As per document it is achieved by below 3 registers.
    DISPC_VID1_BA_j
    DISPC_VID1_PIXEL_INC
    DISPC_VID1_ROW_INC

    I have following questions w.r.t this topic.
    1. How we will know when BA address will be changed so that we can apply below for mirroring ?
    PBA = PBA | (mode << 27) | (orientation << 29) | (1<<32)

    2. What is the value of "mode" & "orientation" in above Point 1 (for 0 degree roatation+ Mirroring)

    3. what will be the value to be used for DISPC_VIDp_PIXEL_INC is it 0x1 ?

    4. What will be the value for DISPC_VID1_ROW_INC, (for 8 bits for pixel)
    ROW0 = 16384: Width of the video picture in memory (in bytes) + 1
    ROW0 = 16384: (730 pixels * 3) + 1
    ROW0 = 16384: 2191 -> What is this mean, what value we need to enter in the register DISPC_VID1_ROW_INC ?

    BR,

    RK

  • Hi RK,

    Could you please refer to the PDK DEI example? In this example, you could find most of these details. 

    You could find this example in ti_components\drivers\pdk_01_10_02_07\packages\ti\drv\vps\examples\vpe\m2mVpeScale\src folder.  Look into M2mVpeScale_utils.c file to understand how image is allocated from tiler memory and how different parameters are set..

    Regards,

    Brijesh