Hi,
I restart a new post related to the same issue because it's not resolved (That's my mistake I closed the post too quick)
https://e2e.ti.com/support/processors/f/791/t/977468
So.. to answer the reply of Brad Griffis:
I agree for the parameter "TIMEPARAGRANULARITY" as the Page mode Successive Data maximum Access Time is defined by the formula: PageBurstAccessTime × (TimeParaGranularity + 1).
But "GPMCFCLKDIVIDER" is not include into the formula. For me, except if I'm wrong, this param allows the GPMC_CLK output to be devided for synchronous devices, but GPMC_FCLK is not affected.
Maybe in synchronous mode, the timing depend on the GPMC_CLK cycle, but I cant use this mode.
I don't read anywhere in the TRM that the timings are based on GPMC_CLK cycles, so even if I change the GPMCFCLKDIVIDER and I reach to reduce the GPMC_CLK, I don't see how it can help to increase the
RdAccessTime...
I forgot to mention that I use a multiplexer in front of the ADC that give 150ns max of transition time.So even if the busy signal is connected to the WAIT input, I need to wait 150ns more before launching a new conversion. This impacts the sample rate that should be reduced to 2.5MHz, the RdAccessTime parameter for the first sample, and once the GPMC module synchronized, the PageBurstAccessTime to be sure that the next address switch when the busy signal is high.
The GPMC EDMA read is asynchrone. The worst case is when the ADC input (ADCIN) is ready to be sampled when the ACQ mode of the ADC is over (red line). So I need to wait for the next ACQ and keep the address unchanged until the next ACQ (during busy signal high).
For the next ACQ, due to the transition time delay, I need to release the address output when the busy signal is high. The address will automatically be kept unchanged (dash lines) until the busy goes low.
Best regards,
Sylvain
