From the technical reference manual I read that MPU_DPLL_CLK is the reference clock for per CPU core watchdog (4.3.6 MPU Watchdog Timer). If I read it correctly, according to the reference manual and the Clock Tree Tool, that signal has a frequency of 20 MHz by default, as it comes directly from SYS_CLK1 and is not divided or multiplied.
When I do not configure a pre-scaler for the watchdog, programming WDT_PRESCALER_REGISTER_i with all 0's, I can see the counter decrementing like expected in the WDT_COUNT_REGISTER_i register. But it seems to be closer to 294 MHz than 20 MHz.
Is it actually MPU_DPLL_CLK that is the input clock to the per CPU core watchdog or am I misunderstanding the configuration and pre-scaler registers?
