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Frequent questions

  • [FAQ] AM62A7-Q1: how to connect the pin net VDDSHV4, VDDSHV5, and VDDSHV6 if SD card is not used

    Part Number: AM62A7-Q1 SD cards is not need in our project using AM62A7-Q1. if SD card is not used, how to connect the pin net VDDSHV4, VDDSHV5, and VDDSHV6 of AM62A7-Q1? leave it open or connected directly to VSS or ?

  • [FAQ] EDGE-AI-STUDIO: Edge AI Resources for AM6xA SoCs

    Part Number: EDGE-AI-STUDIO Texas Instruments has a multitude of resources available for machine learning at the edge (Edge AI). These are spread across ti.com, dev.ti.com (TI Developer Zone + Edge AI Studio), and github. The majority of these resources…

  • [FAQ] PROCESSOR-SDK-AM64X: Accessing DDR from PRU-ICSSG

    Part Number: PROCESSOR-SDK-AM64X Other Parts Discussed in Thread: SYSCONFIG Hi, Can you please help me to access DDR from a PRU core? . The information in this FAQ applies to all Sitara processors with a PRU_ICSSG: AM24x, AM64x, AM65x. The example…

  • [FAQ] Automate the process of code execution through CCS

    Hi, For running a executable through CCS following steps needs to be performed. Open the Code Composer Studio(CCS). Launch the target configuration file. Load the executable to the desired core. Execute the main() function. To…

  • [FAQ] AM623: Trace impedance requirements for EMMC signals

    Part Number: AM623 Hi, As shown in the screenshot, do the signals connected to eMMC have specific impedance requirements?

  • [FAQ]AM64X : How to Route MCU GPIO Interrupts to MAIN Domain Cores in MCU PLUS SDK Version 6.0 & above ?

    Part Number: AM6442 Other Parts Discussed in Thread: SYSCONFIG I am trying to modify the gpio_input_interrupt example for the R5F0-0 core to work with MCU_GPIO0 pins and run it on the R5 core from the CCS debug session, but for now unsuccessfully. …

  • [FAQ] AM64x Profinet: Component Placement Recommendation for SITARA MPU Memory

    Part Number: PROCESSOR-SDK-AM64X Other Parts Discussed in Thread: SYSCONFIG Hi, Can you please recommend how should I perform memory placement of various SW components when using Profinet - TSN on the AM64x processor.

  • [FAQ] How to update IDs (USB & PCIe PID/VID, MAC ID) by programming extended OTP on AM6x

    There are default ID values for the ID registers of USB, PCIe, MAC as listed in the TRM: - PCIe CTRLMMR_PCI_DEVICE_ID0, CTRLMMR_PCI_DEVICE_ID1 - USB CTRLMMR_USB_DEVICE_ID0, CTRLMMR_USB_DEVICE_ID1 - MAC CTRLMMR_MAC_ID0, CTRLMMR_MAC_ID1 The default ID…

  • [FAQ] How to program the extended OTP efuse on AM6x SoC

    Part Number: PROCESSOR-SDK-AM62A K3 SoC (AM64x, AM62x, AM62A...) have a set of One-Time Programmable (OTP) efuses: 1. The user's secure root key set to support Root-of-Trust (RoT) secure boot 2. The extended OTP efuse for general purpose usage by user…

  • [FAQ] How to generate Linux Appimage for Linux SBLs in MCU+ SDK

    Devices covered: AM64x, AM62x, AM62A The Linux SBLs from the MCU+ SDK support booting the Linux from PSDK. These Linux SBLs require a Linux Appimage to boot the Linux. It is noted that this Linux Appimage is generated using the ATF, OPTEE and A53 U…

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