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Frequent questions

  • [FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM625SIP - Collaterals for reference during different phases of custom board design, self-review and bring-up

    Part Number: AM625 Other Parts Discussed in Thread: AM623 , , , AM620-Q1 , SYSCONFIG , SK-AM62B-P1 , SK-AM62-LP , SK-AM62B , SK-AM62-SIP , AM62D-Q1 , AM62X-PET-CALC Hi TI Experts, I am starting a new project and want to use Sitara AM62x processor…

  • [FAQ] TDA4VM: How to do IPC echo test example on TDA4VH/VM

    Part Number: TDA4VM Other Parts Discussed in Thread: TDA4VH Hi Team, How can I build and run IPC Echo test example on TDA4VH boards?

  • [FAQ] AM625 / AM623 / AM625-Q1 / AM620-Q1 / AM62L / AM62A / AM62P / AM62D-Q1 / AM64x / AM243x Custom board hardware design - Processor pin mapping and SK board connections (Supply rail, Capacitors and ferrites)

    Part Number: AM625 Other Parts Discussed in Thread: TMDS64EVM , SK-AM64B , TMDS62LEVM , SK-AM62B-P1 , SK-AM62-LP , SK-AM62B , SK-AM62A-LP , AUDIO-AM62D-EVM , SK-AM62P-LP , SK-AM62-SIP Hi TI Experts, Please provide the SOC power pin mapping and connection…

  • [FAQ] J7200XSOMXEVM: Unable to connect to cluster-1 of MCU R5F and Main R5F in No-boot mode from CCS debugger

    Part Number: J7200XSOMXEVM Other Parts Discussed in Thread: DRA821 After loading the Gel script as described in PSDK RTOS in No Boot Mode, I am unable to connect to the MCU_R5F_0_1 and Main_R5F_0_1 cores.

  • [FAQ] TDA4VM-Q1: How do I resolve build issues in the C66x DSPLIB?

    Part Number: TDA4VM-Q1 Hi Team, I’m encountering build issues while compiling the C66x DSPLIB. Could you help me resolve them? Regards, Betsy Varughese

  • [FAQ] AM62D-Q1: How to modify CPSW resource partitioning for Ethernet Firmware application?

    Part Number: AM62D-Q1 The default out-of-box resource partitioning for AM62Dx distributes CPSW resources between MCU-R5 and A53 core. However, the Ethfw application requires resource distribution between DM-R5, MCU-R5 and A53. How to modify the configuration…

  • [FAQ] J721S2XSOMXEVM: Provide in interface to enable/disable and to configure WDG timer in VHWA modules

    Part Number: J721S2XSOMXEVM This article provides SW interface to enable/disable and to configure watchdog timer for VHWA modules

  • [FAQ] J7200XSOMXEVM: How to enable RGMII interface from both CPSW2G and CPSW5G from U-boot

    Part Number: J7200XSOMXEVM Other Parts Discussed in Thread: J7EXPCXEVM How to enable RGMII Interface from both CPSW instances (CPSW2G from MCU Domain, CPSW5G from Main Domain) supported from J7200.

  • [FAQ] TDA4VL-Q1: How to turn off DebugSS for troubleshooting and/or system requirements

    Part Number: TDA4VL-Q1 I would like to turn off DebugSS, but TISCI API is not turning this off. How can I turn this subsystem off?

  • [FAQ] FAQs of FAQs GPIOs

    Other Parts Discussed in Thread: AM62P , AM62L , AM62D-Q1 , AM625 , AM623 , AM620-Q1 This is a general homepage for FAQs in relation to GPIOs for Sitara devices.

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