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Frequent questions

  • [FAQ] TDA4VM: Switch the DSS configuration from a configuration file between 720p and 1080p

    Part Number: TDA4VM Is there a way to switch the DSS config between 720p and 1080p, after the display has come up and based on the input from the configuration file used for the demo application?

  • [FAQ] 66AK2H14: UART ARM PROJECT

    Part Number: 66AK2H14 How to run UART ARM projects in SDK?

  • [FAQ] AM62x: OSPI in SPI mode for booting, MOSI vs. MISO

    Team, I found the following post regarding Mc SPI boot in SPI mode: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1071789/am62x-mcspi-d0-and-d1-direction-in-spi-bootmode >>> D0 is MISO, and D1 is MOSI. It is not configurable…

  • [FAQ] TDA4VM: Enabling POK Modules

    Part Number: TDA4VM What TDA4VM Power OK (POK) Modules are enabled after reset? Also, how are the individual POK Modules listed in Table 5-1877 of the TDA4VM TRM enabled (please reference screenshot below).

  • [FAQ] TDA4VM: Why does my board enter an abort state after running my application for a long time?

    Part Number: TDA4VM Other Parts Discussed in Thread: SYSBIOS I am running my deep learning application on a custom board for a very long time, but after 2 to 48 hours the deep learning application hangs/freezes and enters an abort state while running…

  • [FAQ] TDA4VM: Clarification on DMIPS calculation for A72

    Part Number: TDA4VM -1- Are you aware of any threads where calculation of DMIPS for an algorithm is discussed for TDA4VM ? -2- I see in TRM “One dual-core 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz and up to 24K DMIPS” 24K…

  • [FAQ] TDA4VM: Maximum pressure or force allowed on package lid of SoC

    Part Number: TDA4VM For the following SoCs: AM57x DRA6x DRA7x DRA8x TDA2x TDA3x TDA4x (And probably any other SoC created by TI, all of which use similar styles of solder balls) FAQ: How much pressure is allowed to be placed onto…

  • [FAQ] TDA4VM: Booting MCU2_1 application form SBL

    Part Number: TDA4VM Hi, Section “6.3.3.2” of TDA4VM TRM states: “ In split mode, each R5F core works completely independent from the other (asymmetric multi-processing, or AMP). Each core uses its own RAMs and interfaces, with no coherence between…

  • [FAQ] 66AK2H12: UART examples for K2H EVM in DSP core

    Part Number: 66AK2H12 How to run UART examples in TI-RTOS SDK for K2H EVM in CCS?

  • [FAQ] Sitara multicore system design: How to ensure computations occur within a set cycle time?

    Part Number: AM6442 I am designing a system with a Sitara multicore device (e.g., AM24x, AM64x, AM65x). The processor needs to complete certain activities within a set cycle time. How do I design my system to make sure that I can meet that cycle time…

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