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Frequent questions

  • [FAQ] AM625: Build DFU enabled U-boot with Yocto for AM62 devices

    Part Number: AM625 Other Parts Discussed in Thread: AM62P , AM62L Overview This article describes how to build and boot DFU enabled U-boot images on TI-K3 devices such as AM62X, AM62A AM62P, AM62L and AM64L using Yocto USB-DFU (Device Firmware Upgrade…

  • [FAQ] AM64x/243x: How to Use Keyring for Authentication of Application Images in MCU+ SDK

    Part Number: AM2434 On HSSE devices, the SYSFW supports the Keyring feature which extends the Root of Trust ( RoT ) to auxiliary keys. This enables the authentication of the application images using these auxiliary keys apart from the programmed SMPKH…

  • [FAQ] AM6XX:How to Port SBL UART UNIFLASH for a custom board

    Part Number: AM62x Other Parts Discussed in Thread: UNIFLASH , AM62P The UART UNIFLASH tool provided in the MCU+SDK will only work for TI EVMs out of the box as it is configured according to Flash and DDR part used in a particular EVM, this FAQ provides…

  • [FAQ] How to boot from dual boot media (OSPI NOR + eMMC) using MCU+SDK?

    Part Number: AM62P Other Parts Discussed in Thread: UNIFLASH Default MCU+SDK SBL examples only support booting from a single boot media (SBL OSPI/SBL EMMC), this FAQ demonstrates how to modify the SBL example to support booting from different boot medias…

  • [FAQ] TDA4VL-Q1: Steps to Build and Run PDK FreeRTOS Example Applications

    Part Number: TDA4VL-Q1 Hello Team, I am looking for guidance on how to build and run the PDK FreeRTOS example applications . Specifically, I would appreciate clarification on the following points: The correct steps to build the PDK FreeRTOS…

  • [FAQ] How to enable the DDR inline ECC in Linux SDK on AM62-SIP board

    Part Number: AM625 DDR ECC [1] on the TI AM62x SoC operates using an inline ECC mechanism. Unlike traditional server-grade systems that require a dedicated 9th memory chip, the AM62x stores Error Correction Code (ECC) data directly within the standard…

  • [FAQ] TDA4AEN-Q1: How to enable 2 different csitx nodes on single instance from openvx application

    Part Number: TDA4AEN-Q1 Other Parts Discussed in Thread: SYSCONFIG The reason behind craeating 2 different nodes for csitx is to transmit frames with different format/resolution on the same csitx instance.

  • [FAQ] TDA4AEN-Q1: TDA4AEN-Q1 : How to configure GPIO1_52-71 (OLDI pins) interrupts on J722S EVM

    Part Number: TDA4AEN-Q1 Other Parts Discussed in Thread: SYSCONFIG , , UNIFLASH The J722S TRM incorrectly states that GPIO1_52 through GPIO1_71 do not support interrupt functionality. In reality, these pins do have interrupt capability but require…

  • [FAQ] TDA4VH-Q1: R5F CCM Pre-requisites and ESM events

    Part Number: TDA4VH-Q1 What do each of the CCM events denote? Are there any pre-requisites before enabling and testing the R5F CCM from SDL?

  • [FAQ] TDA4VH-Q1: Memories tested by PBIST instances on self test

    Part Number: TDA4VH-Q1 I'm looking for detailed information on what memories each PBIST instance performs positive and negative selftest on. All instances don't have same kind of memories. So, I would like to understand what each instance specifically…

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