DM Champs,
We are trying to figure out how we can slice video frames at the capture port. We want to start encoding as soon as we have the first slice of Video in DDR. We are doing this using the DataSync APIs for the H264 encoder.
The encoders need to take the slice data as if it were a normal frame. That is they don't want to do a scatter gather on each slice. The slices need to be contiguous in memory, with the Y data in one buffer and the UV in another buffer.
What we don't have right now, is a reliable way to know if the Capture driver has successfully gotten a slice of data. We only know when it has a full frame. This means we can start processing video until the entire frame is in RAM.
The VIP_PARSER doesn't have any interrupts for horizontal syncs. So I thought I could do it through the DMA engine. However the VPDMA engine outbound descriptors, which is what I think get used for moving data from the VIP_PARSER to DDR, don't seem to have a size field in them. It seems each descriptor applies to a whole frame.
We could try using the embedded sync to switch between channels, and then generate an interrupt as we switch channels. This would require placing a small FPGA in-between the video source and the 8168 which is not super attractive due to size constraints. Its also messy, because we would need to setup the memory writes to get 4:2:0 data into DDR (from a 4:2:2 sources) and have the data nicely overplayed back into the same video buffer.
If this is going to be possible to do, we would need to know if we can somehow create a VPDMA list where we switch descriptors in between slices, and then generate an interrupt. Does this feature exist, or is there another idea about how we could know that the next slice of video has arrived?
Is it possible to get an interrupt directly into the HDVPSS M3 when a certain number of lines of a video field have been transferred to DDR?
