256M memory with dm814x

ranchu

Guru 20755 points

Hello,

I would like to ask if it is possible to work with only one bank of DDR , how to disable one of the banks (for power save) with DM814x

Thank you,

Ran

over 9 years ago

0 Pavel Botev over 9 years ago

TI__Guru**** 170625 points

Hi Ran,

Yes, it is possible to use single EMIF controller with single DDR bank. See the below patch:

processors.wiki.ti.com/index.php

Regards,
Pavel

0 ranchu over 9 years ago in reply to Pavel Botev

Guru 20755 points

Hi Pavel,
It seems that the patch in the link you've provided, is relevant only for PG 1.0, and only for 1Gbytes, Right ?
It seems that it will required more modifications in my case (PG 2.1, 512M, DDR3)

Regards,
Ran

0 ranchu over 9 years ago in reply to ranchu

Guru 20755 points

Hi Pavel,

I've tried to patch my source files according to the FAQ and patch you've provided, but the board fails to start.
It seems that the error is related to the LISA configuration ,
These are the lisa registers I'm using for 256M (singl EMIF) configuration.

/* SINGLE EMIF LISA MAP */
#define MIN_DMM_LISA_MAP__3 0x80500100
....
#ifdef DDR_MEM_512M
__raw_writel(0x80540300, DMM_LISA_MAP__0);
__raw_writel(0xA0540300, DMM_LISA_MAP__1);
__raw_writel(0x80540300, DMM_LISA_MAP__2);

if(USE_EMIF1) {
__raw_writel(0xA0540300, DMM_LISA_MAP__3);
} else {
__raw_writel(MIN_DMM_LISA_MAP__3, DMM_LISA_MAP__3);
}
while (__raw_readl(DMM_LISA_MAP__0) != 0x80540300);
while (__raw_readl(DMM_LISA_MAP__1) != 0xA0540300);
while (__raw_readl(DMM_LISA_MAP__2) != 0x80540300);
while (__raw_readl(DMM_LISA_MAP__3) != 0xA0540300);

#else
.....

I think that the original patch is relevant for 1G only (

#define PG2_1_DMM_LISA_MAP__0 0x0
#define PG2_1_DMM_LISA_MAP__1 0x0
#define PG2_1_DMM_LISA_MAP__2 0x0
#define PG2_1_DMM_LISA_MAP__3 0x80640300

)

Do you have any idea ?

Regards,
Ran

0 Pavel Botev over 9 years ago in reply to ranchu

TI__Guru**** 170625 points

Ran,

Could you try with revert back this patch and apply the below modifications instead of this patch

u-boot/arch/arm/include/asm/arch-ti81xx/ddr_defs_ti814x.h

#define PG2_1_DMM_LISA_MAP__0        0x0
#define PG2_1_DMM_LISA_MAP__1        0x0
#define PG2_1_DMM_LISA_MAP__2        0x0
#define PG2_1_DMM_LISA_MAP__3        0x80400100 0x80640300

u-boot/board/ti/ti8148/evm.c

static void config_ti814x_ddr(void)
{

__raw_writel(0x2, CM_DEFAULT_EMIF_0_CLKCTRL); /*Enable EMIF0 Clock*/
__raw_writel(0x2, CM_DEFAULT_EMIF_1_CLKCTRL); /*Enable EMIF1 Clock*/

/*Poll for Module is functional*/
    while ((__raw_readl(CM_DEFAULT_EMIF_0_CLKCTRL)) != 0x2);
    while ((__raw_readl(CM_DEFAULT_EMIF_1_CLKCTRL)) != 0x2);

0 Pavel Botev over 9 years ago in reply to Pavel Botev

TI__Guru**** 170625 points

#define PG2_1_DMM_LISA_MAP__3 0x80400100 - is for single EMIF0 and 265MB DDR

#define PG2_1_DMM_LISA_MAP__3 0x80500100 - is for single EMIF0 and 512MB DDR

#define PG2_1_DMM_LISA_MAP__3 0x80600100 - is for single EMIF0 and 1GB DDR

0 ranchu over 9 years ago in reply to Pavel Botev

Guru 20755 points

Hi Pavel,

The original configuration I'm using (512M) is as following:

__raw_writel(0x80540300, DMM_LISA_MAP__0);

__raw_writel(0xA0540300, DMM_LISA_MAP__1);

__raw_writel(0x80540300, DMM_LISA_MAP__2);

__raw_writel(0xA0540300, DMM_LISA_MAP__3);

When configuring it as following (without any other modifications in code), it fails:

__raw_writel(0, DMM_LISA_MAP__0);

__raw_writel(0, DMM_LISA_MAP__1);

__raw_writel(0, DMM_LISA_MAP__2);

__raw_writel(0x80500100 , DMM_LISA_MAP__3);

I will now try to add the modification you've described in config_ti814x_ddr(), and see if it makes any differences:

static void config_ti814x_ddr(void)

{

__raw_writel(0x2, CM_DEFAULT_EMIF_0_CLKCTRL); /*Enable EMIF0 Clock*/

__raw_writel(0x2, CM_DEFAULT_EMIF_1_CLKCTRL); /*Enable EMIF1 Clock*/

/*Poll for Module is functional*/

while ((__raw_readl(CM_DEFAULT_EMIF_0_CLKCTRL)) != 0x2);

while ((__raw_readl(CM_DEFAULT_EMIF_1_CLKCTRL)) != 0x2);

...

Thank you very much for the assistance !!

Ran

0 ranchu over 9 years ago in reply to ranchu

Guru 20755 points

Hi Pavel,

The patch works now,

though the u-boot printing still shows me 512M instead of 256M ..........

Thank you very much !!

Ran

0 Pavel Botev over 9 years ago in reply to ranchu

TI__Guru**** 170625 points

Ran,

Ran Shalit said:
though the u-boot printing still shows me 512M instead of 256M ..........

This print is just for info. The default print is for 2GB DDR (by mistake) and fixed to 1GB with the below patch:

Have you tried with modifying ti8148_evm.h like below? This is for single EMIF, 256MB DDR3

#define CONFIG_NR_DRAM_BANKS           1               /* we have 1 bank of DRAM */
#define PHYS_DRAM_1                       0x80000000      /* DRAM Bank #1 */
#define PHYS_DRAM_1_SIZE              0x10000000      /* 256 MB */

0 ranchu over 9 years ago in reply to Pavel Botev

Guru 20755 points

EMIF0 Screen Capture.txt


U-Boot 2010.06-dirty (Mar 24 2015 - 10:56:21)

TI8148-GP rev 3.0

L3 clk         : 200MHz
IVA clk        : 410MHz
ISS clk        : 480MHz
DSP clk        : 750MHz
DSS clk        : 200MHz
ARM clk        : 720MHz
DDR clk        : 400MHz

DRAM:  512 MiB
NAND:  HW ECC BCH8 Selected
512 MiB
Using default environment

The 2nd stage U-Boot will now be auto-loaded
Hit any key to stop autoboot:  0

NAND read: device 0 offset 0x20000, size 0x40000
 262144 bytes read: OK
## Starting application at 0x81000000 ...


U-Boot 2010.06-dirty (Oct 30 2014 - 09:56:38)

TI8148-GP rev 3.0

L3 clk         : 200MHz
IVA clk        : 410MHz
ISS clk        : 480MHz
DSP clk        : 750MHz
DSS clk        : 200MHz
ARM clk        : 720MHz
DDR clk        : 400MHz

------------ PLL Settings --------------
OSC_0_FREQ    : 20MHz

MODENA_N      : 1
MODENA_M      : 72
MODENA_M2     : 1

L3_N          : 19
L3_M          : 800
L3_M2         : 4

DSP_N         : 19
DSP_M         : 750
DSP_M2        : 1

DSS_N         : 19
DSS_M         : 800
DSS_M2        : 4

IVA_N         : 19
IVA_M         : 820
IVA_M2        : 2

ISS_N         : 19
ISS_M         : 960
ISS_M2        : 2

USB_N         : 19
USB_M         : 960
USB_M2        : 5

DCO_HS2_MIN   : 500
DCO_HS2_MAX   : 1000
DCO_HS1_MIN   : 1000
DCO_HS1_MAX   : 2000
SELFREQDCO_HS2   : 2049
SELFREQDCO_HS1   : 4097

--------- DDR PLL ----------
DDR_N             : 0x13
DDR_M             : 0x320
DDR_M2            : 0x2

----------EMIF Timings (identical for 0 & 1)-------
DDR3_EMIF_READ_LATENCY : 0x170209
DDR3_EMIF_TIM1         : 0xAAAD4E3
DDR3_EMIF_TIM2         : 0x40437FDC
DDR3_EMIF_TIM3         : 0x50BF83FF
DDR3_EMIF_REF_CTRL     : 0xC30
DDR3_EMIF_SDRAM_CONFIG : 0x61C051B2
DDR3_EMIF_SDRAM_ZQCR   : 0x50074BE1

----------ranran disbaled the next prints

----------ranran disbaled the next prints

I2C:   ready
DRAM:  512 MiB
NAND:  HW ECC BCH8 Selected
512 MiB
MMC:   OMAP SD/MMC: 0
                          .:;rrr;;.
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           @@s:rrs;5#;;rrrr;r#@H:;;rrsrsrsrsrr:s@@
          @@;;srs&X#9;r;r;;,2@@@rrr:;;rrsrsrsrr;;@@
         @@;;rrsrrs@MB#@@@@@###@@@@@@#rsrsrsrsrr;;@@
        G@r;rrsrsr;#X;SX25Ss#@@#M@#9H9rrsrsrsrsrs;r@G
        @9:srsrsrs;2@;:;;:.X@@@@@H::;rrsrsrsrsrsrr:3@
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       @#;rsrsrsrsrr;r2ir@@@###::rrsrsrsrsrsrsrsrsr:@@
       @A:rrsrsrsrr;:2@29@@M@@@;:;rrrrsrsrsrsrsrsrs;H@
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         @A:rrsrsrsrrrrrsrsrrr;::;@##@r:;rH@h;srr:H@
         ;@9:rrsrsrsrrrsrsrsrsr;,S@Hi@i:;s;MX;rr:h@;
          r@B:rrrrsrsrsrsrsrr;;sA@#i,i@h;r;S5;r:H@r
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                       :ihM#@@@@@##hs,

Net:   Detected MACID:7c:66:9d:35:99:6
cpsw
Hit any key to stop autoboot:  0
HW ECC BCH8 Selected

NAND read: device 0 offset 0x580000, size 0x300000
 3145728 bytes read: OK
## Booting kernel from Legacy Image at 81000000 ...
   Image Name:   Linux-2.6.37
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    2610568 Bytes = 2.5 MiB
   Load Address: 80008000
   Entry Point:  80008000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK
OK

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
Linux version 2.6.37 (ubuntu@ubuntu-laptop) (gcc version 4.5.3 20110311 (prerelease) (GCC) ) #38 Mon Mar 9 16:55:44 IST 2015
CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7f
CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: ti8148evm
bootconsole [earlycon0] enabled
vram size = 52428800 at 0x0
ti81xx_reserve: ### Reserved DDR region @87f00000
reserved size = 52428800 at 0x0
FB: Reserving 52428800 bytes SDRAM for VRAM
Memory policy: ECC disabled, Data cache writeback
OMAP chip is TI8148 3.0
SRAM: Mapped pa 0x402f1000 to va 0xfe400000 size: 0xf000
after smp_prepare_boot_cpu
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 19456
Kernel command line: console=ttyO0,115200n8 ip=10.0.0.2 rw rootdelay=5 ubi.mtd=6,2048 rootfstype=ubifs root=ubi0:rootfs init=/init earlyprintk notifyk.vpssm3_sva=0xBFD00000 mem=128M ddr_mem=512M vram=50M
PID hash table entries: 512 (order: -1, 2048 bytes)
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Memory: 76MB 1MB = 77MB total
Memory: 72080k/72080k available, 58992k reserved, 0K highmem
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    DMA     : 0xffc00000 - 0xffe00000   (   2 MB)
    vmalloc : 0xc8800000 - 0xf8000000   ( 760 MB)
    lowmem  : 0xc0000000 - 0xc8000000   ( 128 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .init : 0xc0008000 - 0xc0035000   ( 180 kB)
      .text : 0xc0035000 - 0xc04eb000   (4824 kB)
      .data : 0xc04ec000 - 0xc053ae40   ( 316 kB)
SLUB: Genslabs=11, HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
NR_IRQS:407
IRQ: Found an INTC at 0xfa200000 (revision 5.0) with 128 interrupts
Total of 128 interrupts on 1 active controller
GPMC revision 6.0
Trying to install interrupt handler for IRQ400
Trying to install interrupt handler for IRQ401
Trying to install interrupt handler for IRQ402
Trying to install interrupt handler for IRQ403
Trying to install interrupt handler for IRQ404
Trying to install interrupt handler for IRQ405
Trying to install interrupt handler for IRQ406
Trying to install type control for IRQ407
Trying to set irq flags for IRQ407
OMAP clockevent source: GPTIMER1 at 20000000 Hz
Console: colour dummy device 80x30
Calibrating delay loop... 719.25 BogoMIPS (lpj=3596288)
pid_max: default: 32768 minimum: 301
Security Framework initialized
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
devtmpfs: initialized
TI81XX: Map 0x87f00000 to 0xfe500000 for dram barrier
TI81XX: Map 0x40300000 to 0xfe600000 for sram barrier
omap_voltage_early_init: voltage driver support not added
regulator: core version 0.5
regulator: dummy:
NET: Registered protocol family 16
omap_voltage_domain_lookup: Voltage driver init not yet happened.Faulting!
omap_voltage_add_dev: VDD specified does not exist!
OMAP GPIO hardware version 0.1
OMAP GPIO hardware version 0.1
OMAP GPIO hardware version 0.1
OMAP GPIO hardware version 0.1
ranran skip omap2_nand_gpmc_retime
ti8148_spi_init [ranran]
NOR: Can't request GPMC CS
after board_nor_init
after phy_register_fixup_for_uid
after ti814x_pcf8575_cir_init
ranran skip ti814x_pcie_pllcfg
ranran remove phy_id update from kernel!
ranran skip ti81xx_init_pcie
clk get on i2c3 fck failed
!!!ti814x_enable_i2c1
clk get on i2c2 fck failed
Cannot clk_get ck_32
Debugfs: Only enabling/disabling deep sleep and wakeup timer is supported now
registered ti81xx_vpss device
registered ti81xx_vidout device
registered ti81xx on-chip HDMI device
registered ti81xx_fb device
registered ti81xx_vin device
NSS Crypto DMA hardware revision 1.9 @ IRQ 116
bio: create slab <bio-0> at 0
vgaarb: loaded
SCSI subsystem initialized
USBSS revision 4ea2080b
registerd cppi-dma Intr @ IRQ 17
Cppi41 Init Done
omap_i2c omap_i2c.1: bus 1 rev4.0 at 400 kHz
I2C: Read failed at pcf8575_cir_enable 263 with error code: -121
I2C: Transfer failed at pcf8575_cir_enable 270 with error code: -121
pcf857x: probe of 1-0021 failed with error -121
regulator: VRTC: 1800 mV
regulator: VIO: 1500 mV
regulator: VDD1: 600 <--> 1500 mV at 1200 mV
regulator: VDD2: 600 <--> 1500 mV at 1200 mV
regulator: VDDCTRL: 600 <--> 1400 mV at 1200 mV
regulator: LDO1: 1100 <--> 3300 mV at 1800 mV
regulator: LDO2: 1100 <--> 3300 mV at 1800 mV
regulator: LDO3: 1100 <--> 3300 mV at 3300 mV
regulator: LDO4: 1100 <--> 3300 mV at 1800 mV
regulator: LDO5: 1100 <--> 3300 mV at 3300 mV
regulator: LDO6: 1100 <--> 3300 mV at 3300 mV
regulator: LDO7: 1100 <--> 3300 mV at 3300 mV
regulator: LDO8: 1100 <--> 3300 mV at 1800 mV
tps65910 1-002d: No interrupt support, no core IRQ
omap_i2c omap_i2c.2: bus 2 rev4.0 at 400 kHz
omap_i2c omap_i2c.4: bus 4 rev4.0 at 400 kHz
Advanced Linux Sound Architecture Driver Version 1.0.23.
Switching to clocksource gp timer
musb-hdrc: version 6.0, peripheral, debug=0
musb-hdrc musb-hdrc.0: dma type: dma-cppi41
MUSB controller-0 revision 4ea20800
usb2phy: computed values rxcalib(15)DACs(25 15 15)
usb2phy: override computed values rxcalib(15)DACs(25 15 15)
usb2phy_config: musb(0) rxcalib done, rxcalib read value 6f6cdf7e
musb-hdrc musb-hdrc.0: USB Peripheral mode controller at c881e000 using DMA, IRQ 18
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 4096 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
TCP reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
NetWinder Floating Point Emulator V0.97 (double precision)
PMU: registered new PMU device of type 0
omap-iommu omap-iommu.0: ducati registered
omap-iommu omap-iommu.1: sys registered
JFFS2 version 2.2. (NAND) � 2001-2006 Red Hat, Inc.
msgmni has been set to 140
alg: No test for stdrng (krng)
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
nss_rng nss_rng: NSS Random Number Generator ver. 2.0
Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
omap_uart.0: ttyO0 at MMIO 0x48020000 (irq = 72) is a OMAP UART0
console [ttyO0] enabled, bootconsole disabled
console [ttyO0] enabled, bootconsole disabled
omap_uart.1: ttyO1 at MMIO 0x48022000 (irq = 73) is a OMAP UART1
omap_uart.2: ttyO2 at MMIO 0x48024000 (irq = 74) is a OMAP UART2
omap_uart.3: ttyO3 at MMIO 0x481a6000 (irq = 44) is a OMAP UART3
omap_uart.4: ttyO4 at MMIO 0x481a8000 (irq = 45) is a OMAP UART4
omap_uart.5: ttyO5 at MMIO 0x481aa000 (irq = 46) is a OMAP UART5
brd: module loaded
loop: module loaded
at24 1-0050: 65536 byte 24c512 EEPROM (writable)
ahci probe: devid name is ahci
ahci CAP register dump =0x6726ff80
Modified ahci CAP register dump =0x6f26ff80
ahci ahci.0: forcing PORTS_IMPL to 0x1
ahci: SSS flag set, parallel bus scan disabled
ahci ahci.0: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
ahci ahci.0: flags: ncq sntf stag pm led clo only pmp pio slum part ccc apst
scsi0 : ahci_platform
ata1: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a150fff] port 0x100 irq 16
m25p80 spi1.0: mb85rs2mt (256 Kbytes)
Creating 1 MTD partitions on "spi_flash":
0x000000000000-0x000000040000 : "FRAM One Partition"
omap2-nand driver initializing
ONFI param page 0 valid
ONFI flash detected
NAND device: Maf ID: 0x2c, Chip ID: 0xac (Micron, NAND 512MiB 1,8V 8-bit)
 erasesize: 0x20000, writesize: 2048, oobsize: 64
omap2-nand: detected x8 NAND flash
Creating 7 MTD partitions on "omap2-nand.0":
0x000000000000-0x000000020000 : "U-Boot-min"
0x000000020000-0x000000260000 : "U-Boot"
0x000000260000-0x000000280000 : "U-Boot Env"
0x000000280000-0x000000580000 : "U-Boot Logo"
0x000000580000-0x0000009c0000 : "Kernel"
0x0000009c0000-0x00000d1e0000 : "File System"
0x00000d1e0000-0x000020000000 : "Reserved"
UBI: attaching mtd6 to ubi0
UBI: physical eraseblock size:   131072 bytes (128 KiB)
UBI: logical eraseblock size:    126976 bytes
UBI: smallest flash I/O unit:    2048
UBI: sub-page size:              512
UBI: VID header offset:          2048 (aligned 2048)
UBI: data offset:                4096
ata1: SATA link down (SStatus 0 SControl 300)
UBI: max. sequence number:       519
UBI warning: print_rsvd_warning: cannot reserve enough PEBs for bad PEB handling, reserved 11, need 16
UBI: attached mtd6 to ubi0
UBI: MTD device name:            "File System"
UBI: MTD device size:            200 MiB
UBI: number of good PEBs:        1601
UBI: number of bad PEBs:         0
UBI: number of corrupted PEBs:   0
UBI: max. allowed volumes:       128
UBI: wear-leveling threshold:    4096
UBI: number of internal volumes: 1
UBI: number of user volumes:     1
UBI: available PEBs:             0
UBI: total number of reserved PEBs: 1601
UBI: number of PEBs reserved for bad PEB handling: 11
UBI: max/mean erase counter: 3/1
UBI: image sequence number:  806041126
UBI: background thread "ubi_bgt0d" started, PID 48
davinci_mdio davinci_mdio.0: davinci mdio revision 1.6
davinci_mdio davinci_mdio.0: detected phy mask fffffffe
davinci_mdio.0: probed
davinci_mdio davinci_mdio.0: phy[0]: device 0:00, driver unknown
CAN device driver interface
CAN bus driver for Bosch D_CAN controller 1.0
d_can d_can: d_can device registered (irq=52, irq_obj=53)
mice: PS/2 mouse device common for all mice
qt602240_ts 1-004a: __qt602240_read_reg: i2c transfer failed
qt602240_ts: probe of 1-004a failed with error -5
omap_rtc omap_rtc: rtc core: registered omap_rtc as rtc0
rtc-rv3049 spi2.1: rtc core: registered rv3049 as rtc1
i2c /dev entries driver
Linux video capture interface: v2.00
OMAP Watchdog Timer Rev 0x00: initial timeout 60 sec
nss_aes_mod_init: loading NSS AES driver
nss-aes nss-aes: NSS AES hw accel rev: 3.2 (context 0 @0x41140000)
nss-aes nss-aes: NSS AES hw accel rev: 3.2 (context 1 @0x41141000)
nss-aes nss-aes: NSS AES hw accel rev: 3.2 (context 2 @0x411a0000)
nss-aes nss-aes: NSS AES hw accel rev: 3.2 (context 3 @0x411a1000)
nss_aes_probe: probe() done
nss_des_mod_init: loading NSS DES driver
nss-des nss-des: NSS DES hw accel rev: 2.2 (context 0 @0x41160000)
nss-des nss-des: NSS DES hw accel rev: 2.2 (context 1 @0x41161000)
nss_des_probe: probe() done
nss_sham_mod_init: loading NSS SHA/MD5 driver
nss-sham nss-sham: NSS SHA/MD5 hw accel rev: 4.03 (context 0 @0x41100000)
nss-sham nss-sham: NSS SHA/MD5 hw accel rev: 4.03 (context 1 @0x41101000)
nss-sham nss-sham: NSS SHA/MD5 hw accel rev: 4.03 (context 2 @0x411c0000)
nss-sham nss-sham: NSS SHA/MD5 hw accel rev: 4.03 (context 3 @0x411c1000)
nss_sham_probe: probe() done

Hi Pavel,

The Linux get freeze when continuing with kernel boot.
Are there any changes required in kernel too ?

Regards,
Ran

0 Pavel Botev over 9 years ago in reply to ranchu

TI__Guru**** 170625 points

Ran,

You can start with adjusting the bootargs for 256MB memory. Try with ddr_mem=256M (not ddr_mem=512M). In EZSDK 256MB map, mem=145M, and MC_HDVPSS_DESC (HDVPSS_DESC) is at 0xAFD00000 (not 0xBFD00000), may be the same is valid here.

Check also DMM_LISA_MAP registers and CM_DEFAULT_EMIF_1_CLKCTRL/CM_DEFAULT_EMIF_1_CLKCTRL registers settings in linux kernel, and align with the u-boot settings.

BR
Pavel

0 ranchu over 9 years ago in reply to Pavel Botev

Guru 20755 points

Hi Pavel,

If I may ask one more about it. We intend to move to 256M.

I think it will also require changed in bld file.

I also see that in memory map AN for the SDK It shows as if DM814x supports only 512M ?

TI8168

• Supports 1GB, 2GB builds

• Linux memory allocated can be 256M or 128M or 512MB for 2GB build

• TI814X

• Supports 512MB build

• Linux memory allocated can be 128M

• TI810X

• Supports 256MB, 512MB builds. Default is 256MB

• Linux memory allocated can be 192/128M for 512MB build & 64M for 256MB build

Thanks,

Ran

0 Pavel Botev over 8 years ago in reply to ranchu

TI__Guru**** 170625 points

Ran,

DM814x EZSDK supports 256MB DDR:
processors.wiki.ti.com/.../EZSDK_Memory_Map

Linux memory allocated is 145MB.

I can not comment regarding DVR RDK.

BR
Pavel

Processors

Processors forum

256M memory with dm814x