About the GFLOPS number of C66x DSP ?

Lets see how they got to this number

If you look at the DSP core you see the following -

The internal connection to the M unit is 128 bit wide, so you can get 4 32-bit values in a cycle. For single precision floating point it is 4 values

The S and L units each has 64 bit internal buses, and each can do 2 32-bit single precision additions

All together there are 8 single precision operations in a single cycle  (look at the  http://www.ti.com/lit/ug/sprugh7/sprugh7.pdf

to see what instructions provide the operations that I specified above)

So 8 floating point instruction per cycle per side in the DSP core

There are two sides - so 16 instructions in a cycle

DSP clock is up to 1.25GHZ so there are 20G instructions per second per core

There are 8 cores and thus we have 160 G floating point instructions in a second or 160 GFLOPS

Ran