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AM3358: Interrupt priority question

alex hoppus
Prodigy 120 points
Part Number: AM3358

Hello!

I mentioned some strange behavior, while playing with baremetal CPSW ethernet driver on beagle bone black.

The described scenario reproduces with ping flood & small packet size, which gives huge amount of CPSW interrupts

Actually, the pattern  looks like:

1. Some code sets INTC_IRQ_THRESHOLD in omap intc to 24

2. CPSW RX interrupt is arriving (irq # 41)

3. In CPSW irq handler I dump interrupt controller registers and see the following:

INTC_SIR_IRQ:                   0x29
INTC_IRQ_PRIORITY:       0x2c
INTC_IRQ_THRESHOLD: 0x18
INTC_ILR 40:                        0x0
INTC_ILR 41:                        0xb0
INTC_ILR 42:                        0xb0
INTC_ILR 43:                        0x0

Which means irq 41 has arrived (0x29) it has priority 44 (0x2c) while priority

threshold is 24 (0x18). According reference manual 6.1.1.4 0x0 is the highest priority,

while 0x7F is the lowest. If so i can't clearly understand: how could we get

IRQ with priority 44, while threshold is was set to 24? Any suggestions about that?

Am i miss something?

Thank you.

  • 0
    TI__Guru**** 393215 points

    Hi,

    From the TRM:

    6.1.1.2.2 Priority Masking

    To enable faster processing of high-priority interrupts, a programmable priority masking threshold is provided (the MPU_INTC.INTC_THRESHOLD[7:0] PRIORITYTHRESHOLD field). This priority threshold allows preemption by higher priority interrupts; all interrupts of lower or equal priority than the threshold are masked.

  • 0 in reply to Biser Gatchev-XID
    Prodigy 120 points
    Sorry, i didn't catch the point. I know that all interrupts of lower priority than the threshold are masked. That is why I'am asking this question. IRQ have priority lower (44) than the threshold (24). Why the irq then was asserted?
  • 0 in reply to alex hoppus
    TI__Guru 71880 points
    Hi Alex, sorry for the late reply. I believe the interrupts of lower priority will only get masked if a higher priority interrupt (higher than the set threshold) is pending or active. If there are no interrupts with a priority above the threshold to service, then ints with priorities with lower or equal thresholds are serviced. The priority threshold register is intended to be used as a preemption mechanism to reduce latency of important interrupts.

    James