Hello, TI Experts,
Our customer sent us questions about GPMC of AM5728.
They want to know the maximum bus access period of GPMC as below condition.
- Asynchronous Read/Write Access
- GPMC_FCLK=266MHz (1clk=about 3.76ns)
Question1:
Based on TRM(SPRUHZ6J) "15.4.4.8.4 Error Handling"
- If GPMC_TIMEOUT_CONTROL.TIMEOUTSTARTVALUE is set to 0x1FF(=511),
a time-out error occurs after over 511 GPMC_FCLK cycles past from the bus access-start.
So, in this case, the effective maximum bus access period is 511xGPMC_FCLK (=about 1.92us).
Is this understanding correct?
Question2:
For read access without wait pin monitoring,
Based on TRM(SPRUHZ6J) "Figure 15-60. Wait Behavior During an Asynchronous Single Read Access"
- The effective maximum bus access period is 31xGPMC_FCLK (=about 116.5ns),
when GPMC_CONFIG5_i.RDCYCLETIME is set to 0x1F(=31).
For Write access without wait pin monitoring, (TRM don't has the appropriate Figure)
- The effective maximum bus access period is 31xGPMC_FCLK (=about 116.5ns),
when GPMC_CONFIG5_i.WRCYCLETIME is set to 0x1F(=31).
Is this understanding correct?
If there are any way of extending bus access other than below, please tell us.
- Configure RDCYCLETIME
- Configure WRCYCLETIME
- wait pin monitoring
Best regards,
