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AM1705: Asynchronous timeout interrupt with extended Wait mode

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Replies: 4

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Part Number: AM1705

Hi,

I'm using Extended Wait Mode (see this issue https://e2e.ti.com/support/processors/f/791/t/797265) with great success.

Now, I am about to start using the EMIFA Asynchronous Time Out Interrupt as described in "AM17x/AM18x ARM Microprocessor External Memory Interface A (EMIFA) User's Guide" (SPRUFVDA), page 45.

When monitoring the EMA_WR and the EMA_WAIT (using an oscilloscope) I can see how the AM1705 starts adding additional cycles when the EMA_WAIT is asserted - just as expected.
When the EMA_WAIT is indefinitely asserted I can see how the AM1705 extends each write access cycle according to what I have specified in MAX_EXT_WAIT (AWCC) - also as expected.

However, the Asynchronous Time Out Interrupt is not issued until after several (20-30) write access cycles have failed to deassert EMA_WAIT.
I would have expected it to be issued at the first write access cycle that fails to deassert EMA_WAIT within the time period specified by MAX_EMA_WAIT.

Could someone please help me understand this.

Thanks,
Michael

4 Replies

  • Hi Michael,

    I've looped in Bill again on this thread... My thoughts are below.

    In cases where the interrupt does not fire, confirm the WAIT signal asserted during the STROBE phase.
    The EMIFA provides configurable cycle timing parameters and an Extended Wait Mode that allows the connected device to extend the strobe period of an access cycle.

    What value is in the MAX_EXT_WAIT field of AWCC? Maximum Extended Wait Cycles = (MAX_EXT_WAIT + 1) × 16

    Are there any other interrupts enabled at the same time?

    An Asynchronous Timeout generates an interrupt, if it has been enabled in the EMIFA interrupt mask set register
    (INTMSKSET).

    Refer to 19.2.8.1 Interrupt Events...

    The asynchronous time out interrupt condition occurs when the attached asynchronous device fails to deassert the EMA_WAIT pin within the number of cycles defined by the MAX_EXT_WAIT bit in AWCC (this happens only in extended wait mode).


    What are the values of the EMIFA interrupt mask set register INTMSKSET and interrupt mask clear register INTMSKCLR?

    Another idea...
    EMIFA interrupt raw register (INTRAW) and the EMIFA interrupt mask register (INTMSK) indicate the status of each interrupt.

    What happens if you poll these registers instead of waiting for the interrupt? The appropriate bit (WR/AT/LT) in INTRAW is set when the interrupt condition occurs, whether or not the interrupt has been enabled

    The appropriate bit (WR_MASKED/AT_MASKED/LT_MASKED) in INTMSK is set only when the interrupt condition occurs and the interrupt is enabled.

    Regards,
    Mark
  • In reply to Mark Mckeown:

    Hi Michael,

    Did you make any progress with this issue? I'll ping Bill about.

    Regards,
    Mark
  • Hi Michael,

    Based on your post, it sounds like the interrupt for the wait time out does occur but not as quickly as you expected. Can you tell us if a single wait time out results in an interrupt at some point in the future? I'm trying to determine if the issue you are reporting is the length of time between the timeout and the interrupt or if a number of timeouts need to occur before the interrupt is generated.

    Regards,

    Bill

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  • In reply to Bill Taboada:

    Hi Michael,

    I haven't seen any posts from you recently. Have you resolved your issue?

    Regards, Bill

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