Tool/software: Linux
Hi,
Out customed Am437x-gp-evm board use three chip selection pins:
1)cs0: NAND;
2)cs2: fpga chip select 0;
3)cs3:fpga chip select 1.
I modified the DT file to add the two fpag chip selections as following:
&gpmc {
/*
* When enabling GPMC, disable eMMC and set
* SelEMMCorNAND to output-low
*/
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x8>;/*<&gpmc_bus_default>;*//*<&nand_flash_x8>*/
ranges = <0 0 0x08000000 0x01000000>, /* CS0 space. Min partition = 16MB */
<2 0 0x01000000 0x01000000>, /* CS2 space, FPGA cs2 */
<3 0 0x02000000 0x01000000>; /* CS3 space, FPGA cs3 */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <40>;
gpmc,cs-wr-off-ns = <40>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <25>;
gpmc,adv-wr-off-ns = <25>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <20>;
gpmc,oe-on-ns = <3>;
gpmc,oe-off-ns = <30>;
gpmc,access-ns = <30>;
gpmc,rd-cycle-ns = <40>;
gpmc,wr-cycle-ns = <40>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x00040000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00040000 0x00040000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00080000 0x00040000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x000c0000 0x00040000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00100000 0x00080000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x00180000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x00280000 0x00040000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x002c0000 0x00040000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00300000 0x00700000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00a00000 0x1f600000>;
};
};
fpga1@1,0 {
compatible = "ti,fram";//cfi-flash";//ti,fram";
#address-cells = <1>;
#size-cells = <1>;
reg = <2 0 0x01000000>; /* CS2 device IO registers */
bank-width=<2>;
gpmc,sync-clk-ps = <10000>; /*Mininum clock period for synchronous mode, in picoseconds */
/*CONFIG1 */ /*100M:10ns*/
gpmc,mux-add-data=<2>;
gpmc,sync-read;/*READTYPE_SYNC */
gpmc,sync-write;/*WRITETYPE_SYNC */
gpmc,wait-pin=<1>;/*wait input pin is WAIT1*/
gpmc,wait-on-read;
gpmc,wait-on-write;
/*CONFIG2 */
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <70>;
gpmc,cs-wr-off-ns = <60>;
/*CONFIG3 */
gpmc,adv-on-ns = <10>;
gpmc,adv-rd-off-ns = <20>;
gpmc,adv-wr-off-ns = <20>;
/*CONFIG4 */
gpmc,oe-on-ns = <30>;
gpmc,oe-off-ns = <60>;
gpmc,we-on-ns = <30>;
gpmc,we-off-ns = <50>;
/*CONFIG5 */
gpmc,rd-cycle-ns = <70>;
gpmc,wr-cycle-ns = <60>;
gpmc,access-ns = <50>; /*rd-access-ns */
gpmc,page-burst-access-ns = <10>;
/*CONFIG 6*/
gpmc,bus-turnaround-ns = <10>;
gpmc,cycle2cycle-delay-ns = <10>;
gpmc,wr-data-mux-bus-ns = <20>;
gpmc,wr-access-ns = <40>;
};
fpga2@2,0 {
compatible = "ti,fram";//cfi-flash";//ti,fram";
#address-cells = <1>;
#size-cells = <1>;
reg = <3 0 0x01000000>; /* CS3 device IO registers */
bank-width=<2>;
gpmc,sync-clk-ps = <10000>; /*Mininum clock period for synchronous mode, in picoseconds */
/*CONFIG1 */ /*100M:10ns*/
gpmc,mux-add-data=<2>;
gpmc,sync-read;/*READTYPE_SYNC */
gpmc,sync-write;/*WRITETYPE_SYNC */
gpmc,wait-pin=<1>;/*wait input pin is WAIT1*/
gpmc,wait-on-read;
gpmc,wait-on-write;
/*CONFIG2 */
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <70>;
gpmc,cs-wr-off-ns = <60>;
/*CONFIG3 */
gpmc,adv-on-ns = <10>;
gpmc,adv-rd-off-ns = <20>;
gpmc,adv-wr-off-ns = <20>;
/*CONFIG4 */
gpmc,oe-on-ns = <30>;
gpmc,oe-off-ns = <60>;
gpmc,we-on-ns = <30>;
gpmc,we-off-ns = <50>;
/*CONFIG5 */
gpmc,rd-cycle-ns = <70>;
gpmc,wr-cycle-ns = <60>;
gpmc,access-ns = <50>; /*rd-access-ns */
gpmc,page-burst-access-ns = <10>;
/*CONFIG 6*/
gpmc,bus-turnaround-ns = <10>;
gpmc,cycle2cycle-delay-ns = <10>;
gpmc,wr-data-mux-bus-ns = <20>;
gpmc,wr-access-ns = <40>;
};
};
the cs2,cs3 is the same only with 'reg' the difference. but the second fpga2 cann't be probed in DT.
root@am437x-evm:~# dmesg |grep gpmc
[ 0.158862] omap-gpmc 50000000.gpmc: could not find pctldev for node /ocp@44000000/l4_wkup@44c00000/scm@210000/pinmux@800/nand_flash_x8, deferring probe
[ 1.443748] omap-gpmc 50000000.gpmc: GPMC revision 6.0
[ 1.448918] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
[ 1.455414] gpio gpiochip4: (omap-gpmc): added GPIO chardev (254:4)
[ 1.455513] gpiochip_setup_dev: registered GPIOs 510 to 511 on device: gpiochip4 (omap-gpmc)
[ 1.456577] of_get_named_gpiod_flags: parsed 'rb-gpios' property of node '/ocp@44000000/gpmc@50000000/nand@0,0[0]' - status (0)
[ 1.835565] omap-gpmc 50000000.gpmc: invalid wait-pin: 1
[ 1.840977] omap-gpmc 50000000.gpmc: failed to probe DT child 'fpga2': -16
root@am437x-evm:~#
the gpmc in am437x.dtsi is:
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
dmas = <&edma 52 0>;
dma-names = "rxtx";
clocks = <&l3s_gclk>;
clock-names = "fck";
reg = <0x50000000 0x2000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
Our SDK version is 05.01.00.11.
Best Regards,
