Hi there,
I have a mature bare-metal application using the AM3358-EP and its Ethernet subsystem (SPRUH73Q TRM chapter 14).
I can create the conditions for an RX DMA stall - whereby the DMA determines there are no buffer descriptors available "cycles before / at the same point" the host adds a new buffer descriptor to the chain.
Most of the time the suggested misqueue detection works well (Chapter 14.4.2 Receive Operation).
In some instances, the suggested "misqueue" detection mechanism fails. I can see that when the host checks the Buffer Descriptor in question, the DMA has not yet set the EOQ flag.
Compiled from the C language, using CPPI memory for BDs, I expected the DMA to be more efficient than the host.
1) When the DMA has determined an EOQ, can it please be confirmed that the DMA will action the Buffer Descriptor at the head descriptor pointer in the following order:
a) check the next pointer is null
b) set EOQ flag
c) clear ownership flag
d) write head descriptor pointer address to completion pointer
e) set head descriptor pointer to zero
2) can it be guaranteed that the DMA will complete the above "stall" in units of time / CPU cycles?
Edit - additional question added below:
3) Are there other mechanisms that would case the RX DMA to stall? The CPSW_STATS registers shows RX DMA Overruns and RX Start Of Frame Overruns both when the misqueue is detected and not detected.
With thanks, Mark