Hi experts,
I am now developing our custom board of TAD4VM with CPSW9G RGMII port. We use a 1000M base-T1 PHY chip (Marvell 88Q2110) to connecting with RGMII6 port.
I have noticed that there is a RO status register (CPSW_SS_RGMII6_STATUS_REG) which shows the current speed / link status. I set the PHY chip working on 1000Mbps / full duplex / Slave mode,but the CPSW_SS_RGMII6_STATUS_REG is 0x3 (half duplex/100Mbsp/link-up). Why this situation happend and how to make RGMII port working at 1000Mbps?
By the way, Marvell 88Q2110 is managed by MDIO Clause 45 and RGMII_RX_CLK is 125MHz but RGMII_TX_CLK is 25MHz.
Thanks and Regards,
Hutian