Intellectual 530 points

Replies: 2

Views: 39

Part Number: TDA4VM

Hi experts,

I am now developing our custom board of TAD4VM with CPSW9G RGMII port. We use a 1000M base-T1 PHY chip (Marvell 88Q2110) to connecting with RGMII6 port.

I have noticed that there is a RO status register (CPSW_SS_RGMII6_STATUS_REG)  which shows the current speed / link status. I set the PHY chip working on 1000Mbps / full duplex / Slave mode,but the CPSW_SS_RGMII6_STATUS_REG is 0x3 (half duplex/100Mbsp/link-up). Why this situation happend and how to make RGMII port working at 1000Mbps?

By the way, Marvell 88Q2110 is managed by MDIO Clause 45 and RGMII_RX_CLK is 125MHz but RGMII_TX_CLK is 25MHz.

Thanks and Regards,


2 Replies

  • Hutian,

    This is interesting and we'd like to understand more on the driver and status through negotiation to help resolve. The PHY driver has traces which can be enabled by setting CpswTrace_runtimeLevel = CPSW_TRACE_DEBUG in <pdk>/packages/ti/drv/cpsw/src/cpsw_trace.c. Can you confirm if you are able to set this in your build and capture the trace output?

    Our PHY driver implementation that we have supports Clause-22 PHYs and we have not tested with Clause-45 PHYs. For C45, we provide only basic MDIO read and write functions, so please do confirm that the Marvell PHY settings are as you expect through initialization.

    The result you are seeing post-autonegotiation is interesting. You are showing 100Mbps HD is reflected in the SoC and the TX clock is 25MHz, which would be expected for that speed, but the RX from the PHY is at 125MHz which would only be expected for 1Gbps. Can you confirm if there is a PHY status register that indicates the link speed and does it match the SoC status? Can you also confirm if you are using the TI PHY driver (cpsw/src/cpsw_phy.c) and its state-machine and what changes have been made to enable C45 PHY?

    Best regards,


  • In reply to Dave Bell:

    Hi Dave,

    I have open the TRACE_DEBUG and using TI PHY driver to enable Marvell PHY.  Currently i can use the RGMII with Marvell PHY to ping with another CPSW9G port, but with some restrict.

    1. The CPSW_MDIO_LINK_REG always show not link, even the Marvell PHY's register shown linked(Clause-45 PHY). I have test in Clause-22 PHY (TJA1102) and it works with the CPSW_MDIO_LINK_REG .

    2. I set the RGMII port in forced mode with 1Gbps and ignore the CPSW_MDIO_LINK_REG, then i can ping with another CPSW9G port on my custom board.

    There is CPSW_MDIO_CLAUS45_REG register. If i setting the mask right for the C45 PHY's address, i can read & write the register's value of the PHY.

    Can you check in which condition the CPSW_MDIO_LINK_REG will shown linked with C45 PHY?