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Original question:

TMS320C6657: Error loading code via JTAG

TMS320C6657: TMS320C6657

Moshe Zach1
Prodigy 130 points
Part Number: TMS320C6657

Hi Rafael,

 

I'm working with Pavel from the DSP board HW side.

I provided here some more information, with addition to what Pavel wrote, the following HW test were done as well:

 

1)      CVDD measured to be 1.1V (although setting to 1.0V probably since the addition of 0.1V by the on board SmartReflex circuit).

2)      CVDD1 was 1.0V

3)      VCC1V8 measured to be 1.8V.

4)      The CoreclockP and N was 100MHz the DSP Sysclock output was measured as expected and we could able to set as required.

5)      The DDRclockP and N was measured and was as expected and we could able to set as required (started with 500MHz, 666MHz etc.

6)      The DSP_RESETZ, DSP_PORZ, DSP_RESETFULLZ, DSP_LRESETNMIENZ signals were "H" level.

7)      The power on sequence of CVDD, CVDD1, 1.8V, CoreClk and reset sequence was measured to be Ok.

8)      All JTAG tests done by the XDS100 v3 were pass successfully.

 

 

The DSP and DDR3 supply pins and GND including the VDDT1, VDDT2, VDDR1, VDDR2 and all DDR3 supplies were connected as in the C6657 lite evm_sch_16-00132-02 schematics.

 

I can add that at the beginning the JTAG test were not pas but after adding serial resistors on the TMS,TDI,TDO, TCK and RCK signals the XDS100 target test was pass successfully.

 

If any additional test or information as schematics for review are required then we can provide it.

Can you suggest other  tests and measurement in HW in order to verify proper work of the HW?

Is the JTAG target test successful pass means that the JTAG communication with the target DSP is reliable and can be trusted?

 

Thanks,

 

Moshe

  • 0
    TI__Mastermind 46460 points

    Moshe,

    The DDRCLOCKP/N should be a frequency like 66MHz or 100MHz.  It should not be 500MHz or 666MHz.  The DDRCLKOUT to the SDRAM will be generated in a PLL and it will be 533MHz or 666MHz.

    What do you mean when you state "all JTAG tests pass"?  Is this just an IR and DR scan check?  If so, this validates that JTAG data can scan through.  You now need to load a GEL file through CCS and then connect to the DSP core(s).

    By using the GEL file, you can initialize the device, program the PLLs and initialize the DDR.  You can check the SYSCLKOUT pin to verify that the main PLL is programmed correctly.  Refer to the KeyStone™ I DDR3 interface bring-up Application Report (SPRACL8) for commissioning the DDR interface.

    Once you have basic functionality with CCS, you should execute tests to perform writes and reads to all of the interfaces to verify robust operation.

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 46460 points

    Moshe,

    Is there any further action needed on this E2E?  If not, I will close it.

    Tom