We have a development with the c6747 processor interfaced on EMIFA to a Xilinx FPGA.
We are using 16bit asynchronous access to do our external access and have CS4 memory space mapped to the FPGA.
We have assigned EMA_BA1 as FPGA_A0, EMA_A0 as FPGA_A1 etc.
The DSP has CE4CFG set for ASIZE 01 (16bit async data bus width).
Everything works fine, except addressing the FPGA appears to need an address shift of x2 added to the base address of CS4.
In other words, to access FPGA register 0x0001 my code has to access address space 0x6400 0002
I can 'scope EMA_BA1 and EMA_A01 for example and confirm this skew is happening. I can't find anything in the data sheets that explicitly states this is required. Am I missing something here?
