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TMS320C6746: Shorting Core Voltage 1.3V to PLLx_VDDA (Voltage Range 1.14 to 1.32) of TMS320C6746

Balaji Appadurai45
Prodigy 200 points
Part Number: TMS320C6746
Other Parts Discussed in Thread: TPS65023

Hi,

We are using Processor P/N#TMS320C6746EZWT4, It is running at 456 MHz and its core supply Voltage is 1.3V.  In our Design, Core Voltage is shorted with PLLx_VDDA, Whereas  PLLx_VDDA voltage Min =1.14V, Typ=1.2 and Max 1.32V

P/N# TPS65023BRSBR is used to supply power for Processor. So the default tolerance of VDCDC1 = 2%. If I do worst case calculation 1.3V +2% = 1.326V (Approximately 6mV more than recommended).

Question

1) At What conditions, VDCDC1 of TPS65023BRSBR can go to +2% (1.326V)? I hope it will be very rare occurrence.

2) Even if VDCDC1 reaches 1.326V, will it impact Process PLLx_VDDA? It is just 6mV excess than the recommended Max voltage. 

Regards,

Balaji A.

  • 0
    TI__Mastermind 30280 points

    Balaji A.,

    It sounds like you are using the DVS feature of the TPS65023 to change VDCDC1 in real time to match the OPP of the processor. When the processor and PMIC coordinate on CPU frequency and regulator voltage, this is referred to as Dynamic Voltage/Frequency Scaling, or DVFS.

    If I am correct, then the processor is changing the DCDC1 voltage using the PMIC driver, which maps the voltage to the operating frequency.

    • For 3.0V, the DEFCORE register (address 0x06) is set to 0x14, or CORE[4..0] = 10100b
    • For 2.75V, the DEFCORE register could be set to 0x13, or CORE[4..0] = 10011b

    The output voltage generated will be accurate wherever the VDCDC1 trace connects to the output path of the DCDC1 regulator. Typically, this feedback path is connect very close to the bulk output capacitor, Cout1, which is also close to the pad of the inductor, Lout1, that connects on the opposite side to the switching node, L1.

    The way the feedback works is that it will never allow this voltage to be less than the target value, which in your case is 3.0V, so the chances that the output voltage of DCDC1 will be >1.30V are higher than the chances of VDCDC1 <1.30V

    The longer the distance from the feedback connection to the point-of-load, the less chance you have of exposing the PLLx_VDDA supply of the processor to >1.326V. The best way to determine the voltage drop from output filter (Cout) to point-of-load (PLLx_VDDA) would be to measure on your PCB. If there is a large voltage drop (20mV, for example) due to trace resistance, you do not have to worry about VDCDC1>1.326V because VPLLx_VDDA = 1.326V - 20mV = 1.306V

    This brings me back to my original point, which is that it would be helpful to understand the minimum allowable Core Voltage for the operating frequency of 456 MHz, which appears to be RVDD at 456MHz = 1.25V Min. This is option 1 below:

    1. If VDCDC1 setpoint is changed to 1.275V (CORE[4..0] = 10011b) using the PMIC driver, then VDCDC1,min = 1.275V * (1 - 0.02) = 1.2495V which rounds up to 1.25V and as I mentioned previously it is more likely the output voltage will be slightly higher than the setpoint (+2% is more likely than -2%). This option may not work if the trace distance to RVDD at the processor is too long (the same voltage drop that helps you for VDCDC1=1.30V will hurt you for VDCDC1=1.275V)
    2. An alternative option would be to set FPWMDCDC1 = 1b in the CON_CTRL Register (address 0x04, bit 1) which improves the output voltage accuracy to +/-1%
    3. Finally, increasing the amount of bulk capacitance at the output will always reduce transients (both positive and negative). If you are concerned, you can increase Cout for DCDC1 and measure the improvement

  • 0 in reply to Brian Berner
    Prodigy 200 points

    Hi Brian,

    Thanks for your response. We have not used I2C to config dynamic voltage Scaling. In fact I2C is just terminated with pull up resistors. This point is already noted for future design improvement when we respin the board. I looked in to PCB in detail, there are some positive points to be considered for this discussion

    1) The trace running from feedback connection to the load PLLx_VDDA is long.

    2)The effective load capacitance is ~75uF at the output. I believe this is more than recommended capacitor value.

    3) From TPS65023BRSBR -VDCDC1 to PLLx_VDD, there is a ferrite bead placed in series. there will be some mV drop here too.

    I hope these factors might have contributed to limit the voltage =<1.32. Moreover, We have not received any complaints with respect to PLL. However, I would like to be more cautious. I too understand that setting FPWMDCDC1 =1b will tighten tolerance from 2% to 1%. Can this tolerance change be done in Hardware as I2C is not connected to Processor in the current design?

    Regards,

    Balaji Appadurai

  • 0 in reply to Balaji Appadurai45
    Prodigy 200 points

    Hi Brian,

    Can the tolerance of DCDCx be reduced from 2% to 1% by Hardware or it has to be done only through I2C by Processor. I kindly request you to respond.

    Regards,

    Balaji A

  • 0 in reply to Balaji Appadurai45
    TI__Mastermind 30280 points

    All settings that can be controlled by the Register Map of the PMIC can only be controlled by I2C, except the starting output voltage of DCDC1, DCDC2, DCDC3 which you can override with the DEFDCDC1-3 pins and the starting voltage of LDO1 & LDO2 which are set by DEFLDO1-2 pins.