TMS320C6678: Clarity Required in Power Consumption Excel Sheet

Hi Binayak

Sorry we dropped the ball on this query. Tom Johnson is no longer with TI , but looks like he has answered similar themed questions from you a few months back and also a couple of years back

Is this a new design? What did you do in 2018 , with similar questions.

I think we have pointed you to the relevant collateral on this. 

I cannot speak much on PDN beyond what Tom responded to - just on the power models , the intent with the baseline is that dominant portion of that is baseline is leakage - apply voltage and no clocks enabled and then followed by clocking / PLL - apply voltage, configure PLLs and enable any module clocks but no modules doing any data movement or processing etc. So there is some "dynamic" aspects in the baselines that can potentially help with load transients and decoupling analysis.

I would recommend following the guidelines in the hardware design guide and look at the TI EVM (which maybe over designed) as a reference to perfect your own hardware design.

Hope this helps. 

Regards

Mukul 

Hi Mukul,

We were planning to use it in one of the projects. However, it was not used then. Hence, we didn't go in depth with it.

(1) As per Tom, baseline current is mostly leakage currents which I'm assuming is DC. In that regard, for considering the CVDD1 current of 2.182A, almost all of it (2.152A) is leakage (DC) with only 30mA for activity. Is it normal for rails to have this much of large leakage current percentage?  

I have two doubts in the recommendations provided on The Hardware Design Guide (sp2abi2d):

(2) It defines a minimum number of capacitors per rail. For CVDD1, it gives for 5W at 1V. How did TI come up with such high power consumption? Even with a realistic maximum utilizations( SP = 25% and CC = 25%) on all eight cores (slightly more than what Tom had recommended), we get only about 2.2W. 

(3) For 5W@1V design, the total current will be 5A. If we follow the activity current and leakage current ratio as in my 2.2W design,  most of the current will be leakage (DC) - only about 100 mA will be activity current. The number of decoupling capacitors recommended is too high for this amount of such small activity current. From hardware design guide, we get a feeling that activity current was not used to recommend the decoupling capacitors. What metric was used then? I am taking activity current as transient current.

Thanks n Regards,

Binayak

Hi Mukul,

We were planning to use it in one of the projects. However, it was not used then. Hence, we didn't go in depth with it.

(1) As per Tom, baseline current is mostly leakage currents which I'm assuming is DC. In that regard, for considering the CVDD1 current of 2.182A, almost all of it (2.152A) is leakage (DC) with only 30mA for activity. Is it normal for rails to have this much of large leakage current percentage?  

I have two doubts in the recommendations provided on The Hardware Design Guide (sp2abi2d):

(2) It defines a minimum number of capacitors per rail. For CVDD1, it gives for 5W at 1V. How did TI come up with such high power consumption? Even with a realistic maximum utilizations( SP = 25% and CC = 25%) on all eight cores (slightly more than what Tom had recommended), we get only about 2.2W.

(3) For 5W@1V design, the total current will be 5A. If we follow the activity current and leakage current ratio as in my 2.2W design,  most of the current will be leakage (DC) - only about 100 mA will be activity current. The number of decoupling capacitors recommended is too high for this amount of such small activity current. From hardware design guide, we get a feeling that activity current was not used to recommend the decoupling capacitors. What metric was used then? I am taking activity current as transient current.

Thanks n Regards,

Binayak

Hi Mukul,

Thanks for your elaborated reply. 

It will be helpful for engineers like us who are designing power distribution system if TI could modify the way it provides the power related information:

Just few suggestions:

(1) It is very difficult for anyone (hardware/software engineer) to guesstimate the SP% and CC%. This is a very important drawback because these affect the CVDD power and current consumption significantly. There should be some other mechanism to get this information rather than guessing.

(2)In result section, instead of providing baseline current and activity current, it will be far useful if TI could provide:

1. dynamic or transient current for decoupling analysis along with the maximum frequency range for board level decoupling effectiveness from when looking outward from the chip;
2. minimum board level target impedance value that can be perceived by the chip;  
3. total current (already provided).

Thanks n Regards,

Binayak