66AK2G12: Ethernet interface is not working in 100mbps

Hi Selva,

Can you share the value of BOOTCFG_ETHERNET_CFG register, located at address 0x02620E20?

I am wondering why you have highlighted few registers (in red) in the dump excel sheet?

Example:

This is "CPSW_P0_RX_MAXLEN" register holding CPPI Port 0 Receive Frame Max Length value. You have highlighted it with "RED".. Did not get what you wanted to communicate here.

Hi Aravind,

Value of BOOTCFG_ETHERNET_CFG Register is  - 2.

The reason for highlighting  some of the register values is to differentiate the register values those who are all different from others. 

thanks & Regards,

selvamuthukumaran. G

Hi Selva,

Thanks.. I see value of 2 is Eth interface mode selection is RGMII, which is correct. 

Can you please explain in detail what sequences are you doing for configuration (1) and how are you setting the 100mpbs (2)?

Snippet from your original post:

1. If we configure the ethernet interface for 100mbps speed the Tx clock in the RGMII line is not changing from 125MHz to 25MHz.
2. Even after setting the 100mbps SW is not Changing RGMII to 100mbps, but it is always fixed at 1G.

I may need to check with local linux experts after I hear from you.

hi Aravind,

we are configuring the ethernet to 100mbps as per the instruction given by the PHY datasheet added the snippet for your reference.

setting the register value as follows,

Register 0 - 1100

register 9 - 0000

Register  0 - 1300

kindly let me know if you have any options other than this to configure the ethernet for 100mbps.

thanks & Regards,

selvamuthukumaran. G

Hi Selva,

Can you please clarify your updates to register 0 and 9? I see only 1100 value that you have shown under Register 0.. It should be 16 bit wide and there are other bits as well.

Also, 

Can you please check the Register 1 (Bit 2) Link status value after you update the register 0, register 9 and register 0 values for auto negotiation for 100Mbps?

I see from PHY spec, register 5 provides the details on link partner's capability. You can read that and check if you are seeing it as capable of 100Mbps.

You can also check if the negotiated speed in CPSW MAC CONTROL register for that port, .

Thanks..

hi Aravind,

the value i mentioned in my last post is in hex. 

setting the register value as follows,

Register 0 - 0x1100

register 9 - 0x0000

Register  0 - 0x1300

i read the PHY register 5 and it shows it is capable of 100mbps speed.

thanks & Regards,

selvamuthukumaran. G

Hi Selva,

Are you getting the link up? Sorry, I can't  provide any more details on the external microchip  PHY part (KSZ9031RNX). All I have same document that you have it.

AFAIK, below sequence would need to be done:

1) set autonegotiation advertise values as recommended in the PHY datasheet (I see you had done this for microchip part)
2) make sure that link is up, one checks LINK bit in BMSR register (Register 1, bit 2: Basic Status register for Link status in PHY chip)
3) Set negotiated speed/duplexity in CPSW_MAC_CONTROL register (K2G SoC)

After that, from K2G, you can check the RGMII status register for link up and speed...

Can you please confirm if you had done above steps? If you still have some issues, I need to check with different team on this.