HARD reset using C6670 Watchdog timer

Hi Piyush,

 So, if nothing happens in CCS and the reset never occurs, that means the watchdog conditions are not met. This causes it to hang. We had an issue with this in a previous example where the watchdog was waiting for 5 interrupts to activate the hard reset, when only one was sent (hece the hang). More details about that in the older forum post here: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/241393.aspx , especially in detail in the last two posts at the bottom.

However, should you may not be using the example code so we can look into this issue in other ways. Can you show the portion of the code where the reset is set and the conditions it is set on? I think that's where we should look for the condition that isn't met.

Good luck!

Kat Kelsch

Hi Kat,

Thank you for replying and sorry for late response.

 I have looked at the example supplied in PDK for C6678 however it does not reset the DSP.

All i want to achieve is, HARD RESET my DSP when watchdog timer times out. I am doing exactly as i explained in start of this post and nothing more. I can see watchdog timer count up and then timeouts. WDFLAG gets set and then nothing. Is there any other register i need to setup to connect WDFLAG and CHIP HARD RESET?

Thanks,

Piyush N. Prince

Hi Piyush,

In the forum post i mentioned, there was an errata in the timer example where it waits for 5 flags to do the hard reset versus just one. You may need to change that in order to make it work. Have you done that?

If you're using the timer example, then you shouldn't need to change the code in any wya to setup the connection from flag to reset. When you say it "times out" do you mean it gets stuck in an infinite loop/wait condition? Or are you saying it errors and stops?

Could you give me an excerpt of what portion of the code it's stopping at? If we can see that then we can see if there is any other reigster we may have forgotten to setup.

Thanks!

Kat Kelsch

Hi Kat,

You can find my code here https://dl.dropbox.com/u/52176145/temp/watchdog.c

I still think there is a missing link in order to connect WDFLAG to trigger HARD RESET.

Thanks.

Piyush

Hi Piyush,

This code seems incomplete. This is just when you setup the timer, but not the section where you are waiting on a reaction. That may be your problem, as I have suggested previously. 

Have you configured your interrupt vector to link the WDFLAG to the HARD RESET in your ISR? (If you don't know what I'm talking about try this training PDF: http://processors.wiki.ti.com/images/d/d6/Swis.pdf  , http://processors.wiki.ti.com/images/b/b2/Hwis.pdf)

-Kat

Hi Kat,

Thank you for your feedback. today i have made a conneciton from CSL_GEM_TINTLN of Interrupt module to WATCHDOG flag (TINTLO). See my updated code here https://dl.dropbox.com/u/52176145/temp/watchdog2.c

I can also confirm, when my watchdog expires TINTLO and WDFLAG will get set in TIMER module also, BIT 0 of EVTFLAG2 (from interrupt module) is getting set. suggest WatchDog flag is not connected to interupt module and still not CHIP reset.

Please note i am not clearing interrupt flag or kicking the watchdog inside the ISR as all i want to do is HARD reset when watchdog barks.

Kind Regrads,

Piyush N. Prince 

Hi Raymond,

Thank you for your response. It works now after setting Reset Mux register correctly. I have pasted my working code below for other forum users.

Kind Regards,

Piyush.

BSLC667X_ErrorCode BSLC667X_Watchdog_Test ( )

{  

BSLC667X_TimerNum_e TimerNumber;

CSL_TmrHandle   hTmr;

CSL_TmrObj      TmrObj;

CSL_Status      Status;

Uint8 CoreId=BSLC667X_GetDspCoreId();

/* Use timer number 0 */

TimerNumber = (BSLC667X_TimerNum_e)( CoreId + (Uint8)BSLC667X_TIMER_NUM_64_0 );

hTmr = BSLC667X_tmrOpen(&TmrObj, TimerNumber, NULL, &Status);

/* Validate opened handle */

if ( (hTmr == NULL) || (Status != CSL_SOK) )       

    return BSLC667X_TICSL_TO_BSLC667X_ERR_MAKE(Status); 

/* Prepare config registers to perform HARD reset when WATCHDOG expires */

/* Unlock kicker */

    *((volatile unsigned int *)(0x02620038)) = 0x83e70b13;

    *((volatile unsigned int *)(0x0262003C)) = 0x95a4f1e0;

/* Configure RESET MUX register RSTMUXx for CORE x to reset COREPAC on watchdog timeout */

    *((volatile unsigned int *)(0x02620308 + (CoreId*4))) = 0xa;

/* RSTCTRL - unlock RSTCFG register */

    *((volatile unsigned int *)(0x023100E8)) = 0x00015a69;

/* RSTCFG - Generate HARD reset when watchdog expires */

    *((volatile unsigned int *)(0x023100EC)) = 0x0;

/* RSTTYP*/

//   *((volatile unsigned int *)(0x023100E4)) = 0x0;
  

/* Lock Kicker */

    *((volatile unsigned int *)(0x02620038)) = 0x0;

    *((volatile unsigned int *)(0x0262003C)) = 0x0;

/* Prepare timer to act as a Watchdog timer */

    hTmr->regs->TCR   = 0x00000000;

    hTmr->regs->TGCR  = 0x0000000B;

    hTmr->regs->CNTHI = 0x00000000;

    hTmr->regs->CNTLO = 0x00000000;

    hTmr->regs->PRDHI = 0x00000001;

    hTmr->regs->PRDLO = 0x00000000;

    *((volatile unsigned int *)(((unsigned int)(&(hTmr->regs->WDTCR)))+0x1c)) = 0x00000001;

/* Start Watchdog timer */

    hTmr->regs->WDTCR = 0xa5c64000;

    hTmr->regs->WDTCR = 0xda7e4000;

/* Close opened handle */

CSL_tmrClose( hTmr );

return BSLC667X_TICSL_TO_BSLC667X_ERR_MAKE(Status);

}